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# System prepended metadata

title: Upstream SIMDe Repo

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Hi everyone,

This is Eric from National Tsing Hua University (NTHU) pllab. This PR includes the initialization of the conversion of Neon to RISC-V Vector Extension (RVV) for SIMDe.

NTHU pllab and Andes Technology have collaborated to convert NEON intrinsics to the RISC-V Vector Extension, and we have converted all NEON intrinsics to RVV intrinsics. This PR marks the beginning of our work. We will soon upstream all of our work.

We made a few changes in the SIMDe repo to suit our needs:

- We modified `type.h` to enable RVV types.
- We modified files related to `memory load & store` due to memory pollution issues in our implementation.
- The initial conversion from Neon to RVV can be viewed in `add.h` and `mul.h`.
- For CI, we've added rvv-qemu in the CI.yml file for RVV testing. The testing runs on a Docker container with Ubuntu 23.10 because we need QEMU 8.0 (which is not available in Ubuntu 22.04). Later, when Ubuntu 24.04 is released on GitHub Actions, testing can be hosted on the Ubuntu 24.04 GitHub Actions machine.

We have included rvv-qemu testing for the following RISC-V V Extension (with ZVFH enabled) architectures:
- `vlen = 128 & elen = 64`
- `vlen = 256 & elen = 64`
- `vlen = 512 & elen = 64`


To compile SIMDe with support for the conversion from NEON to the RISC-V Vector Extension, please use Clang-17 and include the flag ``-mrvv-vector-bits=<vector_length_of_vector_machine>`` during compilation. Replace <vector_length_of_vector_machine> with the actual vector length of RISC-V vector machine.


There's no bug for RVV type