# 資訊科技產業專案設計課程作業 3
[Resume](https://github.com/ORAzzQWQ/Resume/blob/main/resume.pdf)
[Github](https://github.com/ORAzzQWQ)

## 相關工作職缺項目

### [MediaTek](https://careers.mediatek.com/eREC/)
:::spoiler Job Description
#### [數位IC設計工程師_台北](https://careers.qualcomm.com/careers?location=Hsinchu%20City%2C%20Hsinchu%20City%2C%20Taiwan&pid=446700807875&domain=qualcomm.com&sort_by=relevance)

#### 職缺說明
1. Digital design (RTL design, Synthesis, integration, verification)
2. SoC Chip design, integration
3. Familiar with VLSI design flow is a plus

#### 職缺需求
1. Majored in electrical and electronics and Computer Science
2. Experience in VLSI courses is a plus

#### 匹配程度
1. 本身具有RTL design, Synthesis經驗，且也修過DIC、VLSI系統設計課程，但缺乏integration及verification經驗
2. 目前為雙主修資訊系，不確定雙主修是否會被認可
:::

### [Realtek](https://recruit.realtek.com/Job/Search)
:::spoiler Job Description
#### [CPU數位IC驗證工程師](https://recruit.realtek.com/Job/JobDetail?jobid=1479)

#### 職缺說明
Verification for microprocessor designs. Desired skills and experience includes:
1. Experience in processor design verification: test planning, testbench development, and documentation
2. Knowledge of assembly language, C/C++ and/or SystemVerilog
3. Knowledge of SVA or UVM methodology for block and top level verification
4. Formal property checking/formal verification methodologies
5. Proficiency in scripting languages such as Python/Perl

#### 職缺需求
1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。
2. 具相關工作經驗者尤佳。

#### 匹配程度
1. 本身具有撰寫testbench經驗，也會assembly language, C/C++, Python，同時寫過riscv架構的CPU
2. 但本身對SVA or UVM methodology不熟悉
:::

### [NovaTek](https://www.104.com.tw/company/12nopku0?jobsource=cs_2018indexpoc)
:::spoiler Job Description
#### [數位IC設計工程師(I12)](https://www.104.com.tw/job/44wgg?jobsource=cs_2018indexpoc)

#### 職缺說明
1. SoC IC 設計開發, 整合驗證, 量產規劃
2. 高整合 SoC 架構設計與整合規劃 ( Smart TV, FRC)
3. 先進製程 RTL to Netlist 設計流程規劃與實踐 ( low power, synthesis, STA, LINT, CDC)
4. 與 APR 合作, 確認 Placement, CTS, & STA sign-off 品質

#### 職缺需求
1. 電機/電子/通訊/電信工程相關科系
2. 具備數位IC Design Flow: Synthesis / DFT/ STA 驗證經驗者佳
3. 具備 FPGA 驗證經驗者佳
4. 具備影像處理IP設計經驗者佳
5. 具備數位IC產業經驗者佳

#### 匹配程度
1. 本身具有撰寫Synthesis經驗
2. 但本身缺乏SoC架構設計與整合規劃經驗、 先進製程 RTL to Netlist 設計流程規劃與實踐、驗證經驗、影像處理IP設計經驗
:::

### [NVIDIA](https://www.nvidia.com/en-us/about-nvidia/careers/)
:::spoiler Job Description
#### [SOC Design Engineer](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/SOC-Design-Engineer_JR1988424?locationHierarchy1=2fcb99c455831013ea52ed162d4932c0)

#### 職缺說明
1. Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner
1. Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to tackle them
1. Own front-end design quality checks and reviews to present the physical design team with high-quality RTL

#### 職缺需求
1. MS in Computer or Electrical Engineering or equivalent experience
1. 2 plus years of proven experience in chip design, specializing in SOC integration and design automation
1. Excellent analytical and problem-solving skills
1. Experience in RTL design (Verilog), System-On-Chip design/integration flow, and design automation
1. Strong coding skills in Perl, Python, or other industry-standard scripting languages
1. Great communication and teamwork skills to interact within the team and across functional teams to build consensus

#### 匹配程度
1. 本身具有撰寫Verilog經驗
2. 但本身缺乏System-On-Chip design/integration flow, and design automation經驗
:::

---

## 分析
### 數位IC Job
* 對於數位IC相關的職缺來說，有RTL的經驗、SoC、驗證的經驗更為重要
* 有些會看是否有修習相關課程，可能需要盡量符合相關修課
### Self-assessment
* 已修習DIC、VLSI系統設計課程
* 具有開發RISC-V架構CPU的經驗，以及Computer Architecture的背景知識
* 缺乏 SoC架構設計與整合規劃經驗
* 缺乏 驗證經驗、驗證相關課程
* 缺乏 design automation經驗

---

## 模擬面試
:bearded_person:: interviewer :man_with_gua_pi_mao:: interviewee

:bearded_person:: 請說明setup time 及 hold time
:man_with_gua_pi_mao:: Set up time是clock上升前，存進暫存器前需維持一段穩定的時間，才能保證存進暫存器的值沒有問題，這段需維持穩定的時間就稱為set up time，而Hold time是clock上升後，暫存器的值需穩定一段時間，才能保證傳到下一層時的值是正確的，這段穩定的時間就稱為hold time。

:bearded_person:: 請設計一個除頻器，除2倍電路
:man_with_gua_pi_mao:: 請問是同步reset還是非同步reset呢？
:bearded_person:: 非同步reset

:man_with_gua_pi_mao:: 好的，那如果要讓頻率要變一半，周期要變兩倍，所以本來一個clock的時間，變成半個clock的時間。所以每次clock正源觸發時，剛好是0變1、1變0的時機。

module div2 (
  input      clk,
  input      rst_n,
  output reg o_clk
);

always@(posedge clk or negedge rst_n) begin
  if (!rst_n)
    o_clk <= 0;
  else
    o_clk <= ~o_clk;
end

endmodule

:bearded_person:: 那如果我們今天要除4倍電路，請問你可以如何改進？
:man_with_gua_pi_mao:: 如果需要除4的話，我需要加一個計數器來計算

 module div4    (
   input clk,
   input rst_n,
   output reg o_clk
 );

 reg [1:0] cnt;

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n)
     cnt <= 0;
   else if (cnt == 3) // 0 ~ 3
     cnt <= 0;
   else
     cnt <= cnt + 1;
 end

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n)
     o_clk <= 0;
   else if (cnt < 2) // 0 ~ 1
     o_clk = 0;
   else              // 2 ~ 3
     o_clk = 1;
 end
 endmodule

:man_with_gua_pi_mao:: 我利用計數器產生新的clock從0數到3，當0與1時輸出1，而2與3時輸出0
## 參考資料
* [數位IC設計 面試經驗分享](https://www.dcard.tw/f/tech_job/p/240953224)
* [tech talker - 面試經驗分享](https://www.dcard.tw/@techtalker)
* [硅谷老李 - CDC的那些事](https://www.zhihu.com/people/li-hong-jiang-54/posts)
* [如何設計除頻器](https://www.cnblogs.com/oomusou/archive/2008/07/31/verilog_clock_divider.html)