---
# System prepended metadata

title: '[2021/05/13] 數位邏輯設計實習'

---

# [2021/05/13] 數位邏輯設計實習
## EX9
![](https://i.imgur.com/ZRcbTl2.png)

### testbench.sv
```
// Code your testbench here
// or browse Examples
`timescale 1ns/1ns

module testbanch();
  reg [3:0] S;
  reg [4:0] A, B;
  wire [4:0] Alu;
  
  alu4 uut(.S(S), .A(A), .B(B), .Alu(Alu));
  
  initial
    begin
      S = 4'b1101;
      A = 5'b10100;
      B = 5'b00101;      
      #100
      S = 4'b1100;
      #100
      S = 4'b0111;
      #100
      S = 4'b0101;
      #100
      S = 4'b0001;
      #100
      S = 4'b0000;
      #100
      S = 4'b1111;
    end
  
  initial
    begin
      $display("testBanch");
      #700;
      $finish();
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end
endmodule
```

### design.sv
```
// Code your design here
module alu4(S, A, B, Alu);
  input 	[3:0] S;
  input 	[4:0] A, B;
  output	[4:0] Alu;
  reg		[4:0] Alu;

  always@(S or A or B)
    case(S)
      0	: Alu = A>B ? 5'b11111 : 5'b00000;
      1	: Alu = A > B ? A : B;
      5	: Alu = {B[2:0], B[3]};
      7	: Alu = A>>1;
      12: Alu = ~(A^B);
      13: Alu = ~(A & B);
      default: Alu = 6;
    endcase
endmodule
```