# 數位邏輯設計 期末
## 第一題
- testbench.cv

/**Settings
1. Aldec Riviera Pro 2020.04
2. Open EPWave after run if not
*/
`timescale 1ns/1ns

module testbench();

  reg [15:0] D;
  wire Zero, One;

  all_zero_one uut(
    .D(D),
    .Zero(Zero),
    .One(One)
  );

  initial
    begin
      D = 16'ha136;
      #100
      D = 16'h0200;
      #100
      D = 16'hffff;
      #100
      D = 16'h0029;
      #100
      D = 16'h0100;
      #100
      D = 16'h0000;
      #100
      D = 16'h0168;
      #100
      D = 16'h0083;
      #100
      D = 16'h0000;
      #100
      D = 16'h0096;
    end

  initial
    begin
      #1000;
      $stop;
    end

  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end

endmodule

- design.cv

// Code your design here
module all_zero_one(D, Zero, One);
  input [15:0] D;
  output Zero, One;
  reg Zero, One, ZH, ZL, OH,OL;

  always@(D)
    begin
      check_tsk(D[15:8], ZH, OH);
      check_tsk(D[7:0], ZL, OL);
      Zero = ZH & ZL;
      One = OH& OL;
    end


  task check_tsk;
    input [7:0] I;
    output Z,O;

    {Z,O} = {~|I, &I};
  endtask


endmodule

## 第二題
- testbench.cv

// Code your testbench here
// or browse Examples
`timescale 1ns/1ns

module testbanch();
  reg Clk = 1'b0;
  reg Clr = 1'b1;
  wire [11:0] Q;
  
  parameter PERIOD = 500;
  parameter real DUTY_CYCLE = 0.5;
  parameter OFFSET = 0;
  
  initial
  begin
    #OFFSET
    forever
    begin
      Clk = 1'b0;
      #(PERIOD-(PERIOD*DUTY_CYCLE))Clk = 1'b1;
      #(PERIOD*DUTY_CYCLE);
    end
  end
      
  run uut(.Clk(Clk), .Clr(Clr), .Q(Q));
  
  initial
    begin
      #10000
      $stop;
    end
  
  initial
  	begin
      #720;
      Clr = 1'b0;
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end
endmodule

- design.cv

module run (Clk, Clr, Q);
  input 	Clk, Clr;
  output	[10:0] Q;
  reg		[10:0] Q = 0; 

  always@(posedge Clk)
    if(Clr || Q == 10'b1111111111) 
      Q = 0;
  	else 
      if(Q[3:0] == 9)
        begin
          Q[7:4] +=1;
          Q[3:0] = 0;
          if(Q[7:4] == 9)
            begin
              Q[11:8] += 1;
              Q[7:4] = 0;
              if(Q[11:8] == 9)
                Q[11:8] = 0;
            end
        end
  	  else
        Q += 1;
endmodule

## 第三題
- testbench.cv

/**Settings
1. Aldec Riviera Pro 2020.04
2. Open EPWave after run if not
*/
`timescale 1ns/1ns

module test_block();
  
  reg Clk = 1'b0;
  reg Clr = 1'b1;
  reg [4:1] C;
  wire [4:1] R;
  wire [3:0] N;

  parameter PERIOD = 210;
  parameter real DUTY_CYCLE = 0.5;
  parameter OFFSET = 0;

  initial
    begin
      #OFFSET;
      forever
        begin
          Clk = 1'b0;
          #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b1;
          #(PERIOD*DUTY_CYCLE);
        end
    end
  
  kb uut(
    .Clk(Clk),
    .Clr(Clr),
    .C(C),
    .R(R),
    .N(N)
  );
    
  initial
    begin
      C = 16'HF;
      #300
      Clr = 1'b0;
    end
  
  initial
    begin
      #840
      C = 16'H7;
      #840
      C = 16'HB;
      #840
      C = 16'HD;
      #840
      C = 16'HE;
      #840
      C = 16'HF;
    end
  
  initial
    begin
      #5040;
      $stop;
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end
  
endmodule

- design.cv

// Code your design here

module kb(Clk, Clr, C, R, N);
  input Clk, Clr;
  input [4:1] C;
  output [4:1] R;
  output [3:0] N;
  reg [4:1] R = 0;
  reg [3:0] N = 0;
  
  always@(posedge Clk)
    begin
      if(Clr)
        R = 4'b1110;
      else
        R = {R[3:1], R[4]};
      
      case({R, C})
        8'b11101110: N = 16'H0;
        8'b11101101: N = 16'H1;
        8'b11101011: N = 16'H2;
        8'b11100111: N = 16'H3;
        8'b11011110: N = 16'H4;
        8'b11011101: N = 16'H5;
        8'b11011011: N = 16'H6;
        8'b11010111: N = 16'H7;
        8'b10111110: N = 16'H8;
        8'b10111101: N = 16'H9;
        8'b10111011: N = 16'HA;
        8'b10110111: N = 16'HB;
        8'b01111110: N = 16'HC;
        8'b01111101: N = 16'HD;
        8'b01111011: N = 16'HE;
        8'b01110111: N = 16'HF;
        default	   : N = N;
      endcase
    end
endmodule