---
# System prepended metadata

title: '[2021/05/27] 數位邏輯設計實習'

---

# [2021/05/27] 數位邏輯設計實習
## 上課小考
![](https://i.imgur.com/WT4mq7o.png)
### testbench.cv
```
`timescale 1ns/1ns
module go();
  reg Clk= 1'b0;
  reg [3:0]D;
  wire [3:0]Q_1,Q_ff;

  parameter PERIOD = 400;
  parameter real DUTY_CYCLE = 0.5;
  parameter OFFSET = 100;
  
  initial
    begin
      Clk = 1'b0;
      #OFFSET;
      forever
      begin
        Clk = 1'b1;
        #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b0;
        #(PERIOD*DUTY_CYCLE);
      end
    end
  
  gogo uut(
    .Clk(Clk),
    .D(D),
    .Q_1(Q_1),
    .Q_ff(Q_ff)
  );

  initial    
  begin
    D = 5;
    #100
    D = 12;
    #100
    D = 9;
    #100
    D = 1;
    #100
    D = 14;
    #100
    D = 7;
    #100
    D = 9;
    #100
    D = 10;
    #100
    D = 3;
    #100
    D = 6;
    #100
    D = 12;
    #100
    D = 1;
    #100
    D = 8;
    #100
    D = 0;
    #100
    D = 5;
    #100
    D = 12;
    #100
    D = 2;
    #100
    D = 3;
    #100
    D = 10;
    #100
    D = 5;
  end
    
  initial 
  begin
    $display("Starting Testbench...");
    #2000;
    $finish();
  end

  initial 
  begin
    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
endmodule
```
### design.cv
```
module gogo(Clk,D,Q_1,Q_ff);
  input Clk;
  input [3:0]D;
  output [3:0]Q_1,Q_ff;
  reg [3:0]Q_1,Q_ff;
  always@(Clk or D)
    if(Clk)
      Q_1=D;
  always@(posedge Clk)
    Q_ff=D;
endmodule
```

## 上課練習 [dff_1]
### testbench.sv
```
`timescale 1ns/1ns
module testbench();
  reg Clk = 1'b0;
    reg D = 1'b0;
    reg Din = 1'b0;
    reg Clr1 = 1'b1;
    reg Clr2 = 1'b1;
    reg Pre = 1'b0;
    reg Load = 1'b0;
    wire Q1;
    wire Q2;
    wire Q3;
    wire Q4;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for Clk
    begin
        #OFFSET;
        forever
        begin
            Clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    dff_1 UUT (
        .Clk(Clk),
        .D(D),
        .Din(Din),
        .Clr1(Clr1),
        .Clr2(Clr2),
        .Pre(Pre),
        .Load(Load),
        .Q1(Q1),
        .Q2(Q2),
        .Q3(Q3),
        .Q4(Q4));

    initial 
      begin
        // -------------  Current Time:  60ns
        #60;
        D = 1'b1;
        Din = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  260ns
        #200;
        D = 1'b0;
        Din = 1'b1;
        Clr1 = 1'b0;
        Clr2 = 1'b0;
        Pre = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  460ns
        #200;
        D = 1'b1;
        Din = 1'b0;
        Load = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  660ns
        #200;
        D = 1'b0;
        Din = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  860ns
        #200;
        D = 1'b1;
        Din = 1'b0;
        Pre = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  1060ns
        #200;
        D = 1'b0;
        Din = 1'b1;
        Clr1 = 1'b1;
        Clr2 = 1'b1;
        Pre = 1'b1;
        Load = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  1260ns
        #200;
        D = 1'b1;
        Din = 1'b0;
        Clr1 = 1'b0;
        Clr2 = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  1460ns
        #200;
        D = 1'b0;
        Din = 1'b1;
        // -------------------------------------
    end
    
  initial 
  begin
    $display("Starting Testbench...");
    #1800;
    $stop;
    $finish();
  end

  initial 
  begin
    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
endmodule
```
### design.sv
```
// Code your design here
module dff_1(Clk, D, Din, Clr1, Clr2, Pre, Load, Q1, Q2, Q3, Q4);
  input 	Clk, D, Din, Clr1, Clr2, Pre, Load;
  output	Q1, Q2, Q3, Q4;
  reg 		Q1, Q2, Q3, Q4;
  
  always@(posedge Clk)
    Q1 = (Clr1 ? 0 : D);
  
  always@(posedge Clk or posedge Clr2)
    Q2 = (Clr2 ? 0 : D);
  
  always@(negedge Clk or negedge Pre)
    Q3 = (!Pre ? 1 : D);
  
  always@(negedge Clk)
    Q4 = (!Load ? Din : D);
  
endmodule
```