---
# System prepended metadata

title: '[2021/05/20] 數位邏輯設計實習'

---

# [2021/05/20] 數位邏輯設計實習
## 上課小考
![](https://i.imgur.com/quBfQSW.png)
- testbench.cv
```
// Code your testbench here
// or browse Examples
`timescale 1ns/1ns

module testbanch();
  reg [3:0] D;
  wire [6:0] Q1, Q2;
  
  dec7_seg uut(.D(D), .Q1(Q1), .Q2(Q2));
  
  initial
    begin
      D = 0;   
      #100
      D = 1; 
	  #100
      D = 2;
      #100
      D = 3;
      #100
      D = 4;
      #100
      D = 5;
      #100
      D = 6;
      #100
      D = 7;
      #100
      D = 8;
      #100
      D = 9;
      #100
      D = 10;
      #100
      D = 11;
      #100
      D = 12;
      #100
      D = 13;
      #100
      D = 14;
      #100
      D = 15;
    end
  
  initial
    begin
      $display("testBanch");
      #1600;
      $finish();
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end
endmodule
```
- design.cv
```
// Code your design here
module dec7_seg(D, Q1, Q2);
  input 		[3:0] D;
  output 		[6:0] Q1, Q2;
  reg			[6:0] Q1, Q2;

  always@(D)
    if(D == 0) 			Q1 = ~7'b1111110;
    else if(D == 1) 	Q1 = ~7'b0110000;
    else if(D == 2) 	Q1 = ~7'b1101101;
    else if(D == 3) 	Q1 = ~7'b1111001;
    else if(D == 4) 	Q1 = ~7'b0110011;
    else if(D == 5) 	Q1 = ~7'b1011011;
    else if(D == 6) 	Q1 = ~7'b1011111;
    else if(D == 7) 	Q1 = ~7'b1110010;
    else if(D == 8) 	Q1 = ~7'b1111111;
    else if(D == 9) 	Q1 = ~7'b1111011;
    else if(D == 10) 	Q1 = ~7'b1110111;
    else if(D == 11) 	Q1 = ~7'b0011111;
    else if(D == 12) 	Q1 = ~7'b1001110;
    else if(D == 13) 	Q1 = ~7'b0111101;
    else if(D == 14) 	Q1 = ~7'b1001111;
    else				Q1 = ~7'b1000111;
  
  always@(D)
    case(D)
      0: 		Q2 = ~7'b1111110;
      1: 		Q2 = ~7'b0110000;
      2: 		Q2 = ~7'b1101101;
      3: 		Q2 = ~7'b1111001;
      4: 		Q2 = ~7'b0110011;
      5: 		Q2 = ~7'b1011011;
      6: 		Q2 = ~7'b1011111;
      7: 		Q2 = ~7'b1110010;
      8: 		Q2 = ~7'b1111111;
      9: 		Q2 = ~7'b1111011;
      10: 		Q2 = ~7'b1110111;
      11: 		Q2 = ~7'b0011111;
      12: 		Q2 = ~7'b1001110;
      13: 		Q2 = ~7'b0111101;
      14: 		Q2 = ~7'b1001111;
      default: 	Q2 = ~7'b1000111;
    endcase
endmodule
```

## 上課練習
### [ent0] 課本
- testbench.cv
```
// Code your testbench here
// or browse Examples
`timescale 1ns/1ns

module testbanch();
  reg Clk = 1'b0;
  reg Pre = 1'b0;
  wire [2:0] D;
  
  parameter PERIOD = 200;
  parameter real DUTY_CYCLE = 0.5;
  parameter OFFSET = 0;
  
  initial
  begin
    #OFFSET
    forever
    begin
      Clk = 1'b0;
      #(PERIOD-(PERIOD*DUTY_CYCLE))Clk = 1'b1;
      #(PERIOD*DUTY_CYCLE);
    end
  end
      
  ent0 uut(.Clk(Clk), .Pre(Pre), .D(D));
  
  initial
    begin
      #2200
      $stop;
    end
  
  initial
  	begin
      #85;
      Pre = 1'b1;
    end
  
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0);
    end
endmodule
```
- design.cv
```
// Code your design here
module ent0(Clk, Pre, D);
  input 	Clk, Pre;
  output 	[2:0] D;
  reg		[2:0] D;

  always@(posedge Clk or negedge Pre)
    D = (!Pre ? ~Pre : D+1);
      
endmodule
```
### [ent0] BREND
```