# [2021/06/10] 數位邏輯設計實習
## 上課小考EX16
- BREND
### testbench.cv

    `timescale 1ns/1ns

    module testbench;
      reg Clk = 1'b0;
      reg Clr = 1'b0;
      reg Up = 1'b0;
      wire A;
      wire B;
      wire C;
      wire D;
      wire E;
      wire F;
      wire G;

      parameter PERIOD = 200;
      parameter real DUTY_CYCLE = 0.5;
      parameter OFFSET = 0;

      initial   
        begin
          #OFFSET;
          forever
          begin
            Clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
          end
        end

      run uut (
        .Clk(Clk),
        .Clr(Clr),
        .Up(Up),
        .A(A),
        .B(B),
        .C(C),
        .D(D),
        .E(E),
        .F(F),
        .G(G)
      );

      initial
        begin
          #285
          Clr = 1'b1;
          #1315
          Up = 1'b1;
        end

      initial
        begin
          $display("Starting Testbench...");
          #3200
          $stop;
          $finish();
        end

      initial 
        begin
          $dumpfile("dump.vcd");
          $dumpvars(0);
        end

    endmodule

### design.cv

    module run (Clk, Clr, Up, A, B, C, D, E, F, G);
      input 	Clk, Clr, Up;
      output	A, B, C, D, E, F, G;
      reg		[2:0] Q;
      reg		[6:0] L;


      always@(negedge Clk)
        if(!Clr) Q = 0;
        else Q = (Q)%4 + 1;

      always@(Q or Up)
        case(Q)
          1			: L = (Up == 1'b1 ? 7'b1100111 : 7'b0110111); // b1100111:67 / b0110111:37
          2			: L = (Up == 1'b1 ? 7'b0110111 : 7'b1100111); // b0110111:37 / b1100111:67
          3			: L = (Up == 1'b1 ? 7'b1100111 : 7'b0110111); // b1100111:67 / b0110111:37
          4			: L = (Up == 1'b1 ? 7'b1111001 : 7'b1011111); // b1111001:79 / b1011111:5f
          default		: L = 7'b0001110;
        endcase

      assign {A, B, C, D, E, F, G} = L;
    endmodule