# [2021/06/03] 數位邏輯設計實習
## 上課小考EX13
- 樹懶ww
### testbench.cv

    `timescale 1ns/1ns
    module go();
      reg Clk,T,Pre,Clr,Load,D;
      wire Q;

      parameter PERIOD = 200;
      parameter real DUTY_CYCLE = 0.5;
      parameter OFFSET = 100;

      initial
        begin
          Clk = 1'b1;
          #OFFSET;
          forever
          begin
            Clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) 
            Clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
          end
        end

      gogo uut(
        .Clk(Clk),
        .T(T),
        .D(D),
        .Pre(Pre),
        .Clr(Clr),
        .Load(Load),
        .Q(Q)
      );

      initial    
      begin
      //要寫自己的
        T = 1;    
        Pre = 1;
        Clr = 1;
        Load =1;
        D = 1;
        #200
        Pre = 0;
        Clr = 1;
        Load =1;
        #200
        Pre = 0;
        Clr = 0;
        Load =1;
        #200
        Load =0;
        #200
        T = 0;
        #100
        T = 1;
        #100
        T = 0;

      end

      initial 
      begin
        $display("Starting Testbench...");
        #1100;
        $finish();
      end

      initial 
      begin
        $dumpfile("dump.vcd");
        $dumpvars(0);
      end
    endmodule

### design.cv

    module gogo(Clk,T,D,Pre,Clr,Load,Q);
      input Clk,T,Pre,Clr,Load,D;
      output Q;
      reg Q;
      always@(negedge Clk or posedge Pre)
        if(Pre) 		Q=1;
        else if(Clr)	Q=0;
        else if(Load)	Q=D;
        else if(T==1)	Q=~Q;
        else 			Q=Q;    
    endmodule

- 上課小考 - BREND
### testbench.cv

    `timescale 1ns/1ns
    module testbench();
      reg 	Clk= 1'b0, Clr, Pre, Load, T;
      reg 	D;
      wire 	Qt;

      parameter PERIOD = 200;
      parameter real DUTY_CYCLE = 0.5;
      parameter OFFSET = 100;

      initial
        begin
          Clk = 1'b0;
          #OFFSET;
          forever
          begin
            Clk = 1'b1;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b0;
            #(PERIOD*DUTY_CYCLE);
          end
        end

      dff_2 uut(
        .Clk(Clk),
        .D(D),
        .T(T),
        .Clr(Clr),
        .Pre(Pre),
        .Load(Load),
        .Qt(Qt)
      );

      initial    
      begin
        T = 1;    
        Pre     = 0;
        Clr     = 0;
        Load    = 1;
        D = 1;
        #200
        Pre     = 0;
        Clr     = 1;
        Load    = 1;
        #200
        Pre     = 1;
        Clr     = 1;
        Load    = 1;
        #200
        Load =0;
        #200
        T = 0;
        #100
        T = 1;
        #100
        T = 0;
      end

      initial 
      begin
        $display("Starting Testbench...");
        #1000;
        $stop;
        $finish();
      end

      initial 
      begin
        $dumpfile("dump.vcd");
        $dumpvars(0);
      end
    endmodule

### design.cv

    // Code your design here

    module dff_2(Clk, D, T, Clr, Pre, Load, Qt);
      input 	Clk, D, T, Clr, Pre, Load;
      output 	Qt;
      reg		Qt;

      always@(negedge Clk or posedge Pre or posedge Clr)
        if(Pre)			Qt = 1;
        else if(Clr)	Qt = 0;
        else if(Load)	Qt = D;
        else if(T==1)		Qt=~Qt;
        else 				Qt=Qt;
    endmodule

## 上課練習EX14
- BREND
### testbench.cv

    `timescale 1ns/1ps

    module testbench;
      reg Clk = 1'b0;
      reg Load = 1'b1;
      wire [3:0] Q;
      wire A;
      wire B;
      wire C;
      wire D;
      wire E;
      wire F;
      wire G;
      wire [6:0] L;

      parameter PERIOD = 200;
      parameter real DUTY_CYCLE = 0.5;
      parameter OFFSET = 0;

      initial   
        begin
          #OFFSET;
          forever
          begin
            Clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
          end
        end

      cnt4 uut (
        .Clk(Clk),
        .Load(Load),
        .Q(Q),
        .A(A),
        .B(B),
        .C(C),
        .D(D),
        .E(E),
        .F(F),
        .G(G),
        .L(L)
      );

      initial
        begin
          #285
          Load = 1'b0;
        end

      initial
        begin
          $display("Starting Testbench...");
          #2600
          $stop;
          $finish();
        end

      initial 
        begin
          $dumpfile("dump.vcd");
          $dumpvars(0);
        end

    endmodule

### design.cv

    module cnt4 (Clk,Load,Q,A,B,C,D,E,F,G,L);
      input  Clk,Load;		
      output [3:0] Q;			
      output A,B,C,D,E,F,G;	
      output [6:0] L;			
      reg    [3:0] Q;			
      reg    [6:0] L;		
  
      always@(posedge Clk) 
        if (Load)     	Q = 9;
        else if (Q == 0)	Q = 0;
        else	       		Q = Q - 1;
  
      always@(Q) 
        case (Q)
          0      : L = 7'h7e;
          1      : L = 7'h30;
          2      : L = 7'h6d;
          3      : L = 7'h79;
          4      : L = 7'h33;
          5      : L = 7'h5b;
          6      : L = 7'h1f;
          7      : L = 7'h70;
          8      : L = 7'h7f;
          9      : L = 7'h73;
          default: L = 7'h00;
        endcase
  
      assign {A,B,C,D,E,F,G} = L;

    endmodule

## 上課練習EX15
- BREND
### testbench.cv

    `timescale 1ns/1ns

    module testbench;
      reg Clk = 1'b0;
      reg Clr = 1'b1;
      wire A;
      wire B;
      wire C;
      wire D;
      wire E;
      wire F;

      parameter PERIOD = 200;
      parameter real DUTY_CYCLE = 0.5;
      parameter OFFSET = 0;

      initial   
        begin
          #OFFSET;
          forever
          begin
            Clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) Clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
          end
        end

      pili_1 uut (
        .Clk(Clk),
        .Clr(Clr),
        .A(A),
        .B(B),
        .C(C),
        .D(D),
        .E(E),
        .F(F)
      );

      initial
        begin
          #285
          Clr = 1'b0;
        end

      initial
        begin
          $display("Starting Testbench...");
          #3200
          $stop;
          $finish();
        end

      initial 
        begin
          $dumpfile("dump.vcd");
          $dumpvars(0);
        end

    endmodule

### design.cv

    module pili_1 (Clk, Clr, A, B, C, D, E, F);
      input 	Clk, Clr;
      output	A, B, C, D, E, F;
      reg		[6:0] L;


      always@(posedge Clk)
        if(Clr)					L = 7'b1000000;
      else if(L == 7'b1000000)	L = 7'b0100000;
      else if(L == 7'b0100000)	L = 7'b0010000;
      else if(L == 7'b0010000)	L = 7'b0001000;
      else if(L == 7'b0001000)	L = 7'b0000100;
      else if(L == 7'b0000100)	L = 7'b0000010;
      else if(L == 7'b0000010)	L = 7'b1000001;
      else if(L == 7'b1000001)	L = 7'b0000011;
      else if(L == 7'b0000011)	L = 7'b0000101;
      else if(L == 7'b0000101)	L = 7'b0001001;
      else if(L == 7'b0001001)	L = 7'b0010001;
      else if(L == 7'b0010001)	L = 7'b0100001;
      else if(L == 7'b0100001)	L = 7'b1000000;
      else 						L = 7'b0000000;

      assign {A, B, C, D, E, F} = L[6:1];
    endmodule