---
# System prepended metadata

title: 數位邏輯設計實習 期末準備

---

# 數位邏輯設計實習 期末準備
## 10-6七段多工顯示之時分秒計時器
- design.cv
```
module timer_7seg(Clk10M, Clr, De, A, B, C, D, E, F, G);
  input Clk10M, Clr;
  output [3:1] De;
  output A, B, C, D, E, F, G;
  
  reg [7:0] H, M, S;
  reg [23:0] Q;
  reg [3:0] Code;
  reg Clk1;
  reg [6:0] L;
  
  
  // 除頻1Hz
  always@(posedge Clk10M)
    begin
      if(Clr || Q == 9999999)
        Q = 0;
      else
        Q += 1;
      Clk1 = Q[23];
    end
  
  // 取得多工顯示頻率 ~ 300Hz
  assign De = Q[14:12];
  
  // 產生計時器
  always@(posedge Clk1)
    if(Clr)
      begin 
        H = 0;
        M = 0;
        S = 0;
      end
  else if(S[3:0] == 4'h9)
    begin
      S[7:4] += 1;
      S[3:0] = 0;
      if (S == 8'h59)
        begin
          M[3:0] += 1;
          S = 0;
          if(M[3:0] == 4'h9)
            begin
              M[7:4] += 1;
              M[3:0] = 0;
              if(M == 8'h59)
                begin
                  H[3:0] += 1;
                  M = 0;
                  if(H[3:0] == 4'9)
                    begin
                      H[7:4] += 1;
                      H[3:0] = 0
                      if(H == 8'h24)
                        begin
                          H = 0;
                        end
                    end
                end
            end
        end
    end
  else 
    S[3:0] += 1;
  
  //七段多工十進制碼，組合邏輯電路
  always@(De or H or M or S)
    case(De)
      0			: Code = H[7:4]; // 3'b000
      1			: Code = H[3:0]; // 3'b001
      2			: Code = M[7:4];
      3			: Code = M[3:0];
      4			: Code = S[7:4];
      5			: Code = S[3:0];
      default 	: Code = 0;
    endcase
  
  // 七段顯示，組合電路
  always@(Code)
    case(Code)
      0: 		L = 7'h73;
      1: 		L = 7'h30;
      2: 		L = 7'h6d;
      3: 		L = 7'h79;
      4: 		L = 7'h33;
      5: 		L = 7'h5b;
      6: 		L = 7'h1f;
      7: 		L = 7'h70;
      8: 		L = 7'h7f;
      9: 		L = 7'h73;
      default: 	L = 7'h00;
    endcase
  
  assign {A, B, C, D, E, F, G} = L;
endmodule
```

## 電子骰子遊戲
- design.cv
```
module dice(Clk10M, Start, Led);
  input Clk10M, Start;
  output [6:0] Led;
  
  reg [6:0] Led;
  reg [20:0] Cnt1;
  reg [5:0] Cnt2;
  reg [1:0] State;
  reg Clk, Dice_clk;
  
  
  // 除頻1Hz
  always@(posedge Clk10M)
    begin
      Cnt1 += 1;
      Clk = Cnt1[15];
    end
    
  // 產生計時器
  always@(posedge Clk1)
    if(Start == 0)
      begin
        State = 3;
        Cnt2 = 0;
      end
  	else
      begin
        Cnt2 += 1;
        if(Cnt2 == 6'b111111)
          State -= (State>0);
      end
  
  // 骰子顯示頻率
  always@(State)
    case(State)
      3: Dice_clk = Cnt1[18];
      2: Dice_clk = Cnt1[19];
      1: Dice_clk = Cnt1[20];
      default: Dice_clk = 0; // 骰子停止
    endcase
   
  // 骰子LED值顯示
  always@(posedge Dice_clk)
    case(Led)
      7'b0001000	: Led = 7'b0100010;
      7'b0100010	: Led = 7'b0011100;
      7'b0011100	: Led = 7'b1010101;
      7'b1010101	: Led = 7'b1011101;
      7'b1011101	: Led = 7'b1110111;
      default		: Led = 7'b0001000;
    endcase
endmodule
```

## 三色點矩陣顯示多工掃描
- design.cv
```
module dot_mx(Clk10M, Row, Cr, Cg);
  input Clk10M,;
  output [1:8] Row, Cr, Cg;
  
  reg [1:8] Row, Cr, Cg;
  reg [25:0] Q;
  reg Clk;
  
  // 除頻
  always@(posedge Clk10M)
    begin
      Q += 1;
      Clk = Q[11];
    end
    
  // 產生計時器
  always@(posedge Clk1)
    case(Row)
      8'b00000001	: Row = 8'b10000000;
      8'b10000000	: Row = 8'b01000000;
      8'b01000000	: Row = 8'b00100000;
      8'b00100000	: Row = 8'b00010000;
      8'b00010000	: Row = 8'b00001000;
      8'b00001000	: Row = 8'b00000100;
      8'b00000100	: Row = 8'b00000010;
      default		: Row = 8'b00000001;
  
  // 骰子顯示頻率
   always@(Q[24] or Q[25] or Row)
     if(Q[24] == 1)
       case(Row)
         8'b10000000	: Cr = 8'b00010000;
         8'b01000000	: Cr = 8'b00100010;
         8'b00100000	: Cr = 8'b01000100;
         8'b00010000	: Cr = 8'b11011111;
         8'b00001000	: Cr = 8'b01010001;
         8'b00000100	: Cr = 8'b01001010;
         8'b00000010	: Cr = 8'b01000100;
         8'b00000001	: Cr = 8'b01011111;
         default		: Cr = 8'b00000000;
       endcase
     else
       Cr = 8'b00000000;
   	if(Q[25] == 1)
       case(Row)
         8'b10000000	: Cg = 8'b00010000;
         8'b01000000	: Cg = 8'b00100010;
         8'b00100000	: Cg = 8'b01000100;
         8'b00010000	: Cg = 8'b11011111;
         8'b00001000	: Cg = 8'b01010001;
         8'b00000100	: Cg = 8'b01001010;
         8'b00000010	: Cg = 8'b01000100;
         8'b00000001	: Cg = 8'b01011111;
         default		: Cg = 8'b00000000;
       endcase
     else
       Cg = 8'b00000000;
   end
endmodule
```

## LCD液晶顯示模組
```
module LCM(Clk10M, Clr, EN. RS, RW, D, Cs);
  input Clk10M, Clr;
  output EN, RS, RW;
  output [7:0] D;
  output [2:0] Cs;
  reg Clk, Clk_en;
  reg [7:0] D;
  reg [23:0] Cnt;
  reg [1:0] Cn;
  reg [2:0] Cs, Ns;
  parameter [2:0] S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
  
  // 除頻
  always@(posedge Clk10M)
    begin
      if(Clr)
        Cnt = 0;
      else
        Cnt += 1;
      Clk = Cnt[23];
      // Clk = Cnt[0]; // 模擬用
    end
  
  always@(posedge Clk or posedge Clr)
    begin
      if(Clr)
        begin
          Cn = 0;
          Cs = 3'b000;
        end
      else if(Cn == 2'b10)
        begin
          Cn = 0;
          Cs = Ns;
        end
      else
        Cn += 1;
      Clk_en = Cn[0];
    end
    
  always@(Cs)
    case(Cs)
      S0: begin
        Ns = S1;
        D = 8'b00111000;
      end
      S1: begin
        Ns = S2;
        D = 8'b00111000;
      end
      S2: begin
        Ns = S3;
        D = 8'b00001110;
      end
      S3: begin
        Ns = S4;
        D = 8'b00001110;
      end
      S4: begin
        Ns = S5;
        D = 8'b00000001;
      end
      S5: begin
        Ns = S6;
        D = 8'b11000100;
      end
      S6: begin
        Ns = S7;
        D = 8'b01000001;
      end
      S7: begin
        Ns = S7;
        D = 8'b00000000;
      end
    endcase
  
  assign EN = (Cs == S7 ? 0 : Clk_en);
  
  assign RS = (Cs == S6 ? 1 : 0);
  
  assign RW = 0;
  
endmodule
```