---
# System prepended metadata

title: '[2021/06/17] 數位邏輯設計實習'

---

# [2021/06/17] 數位邏輯設計實習
## 上課小考EX17
![](https://i.imgur.com/rxVXu2g.png)

- BREND
    ![](https://i.imgur.com/qY1XUl9.png)
    ### testbench.cv
    ```
    /**Settings
    1. Aldec Riviera Pro 2020.04
    2. Open EPWave after run if not
    */
    `timescale 1ns/1ns

    module testbench();

      reg [7:0] D;
      wire Zero, One;

      all_zero_one uut(
        .D(D),
        .Zero(Zero),
        .One(One)
      );

      initial
        begin
          D = 95;
          #100
          D = 200;
          #100
          D = 0;
          #100
          D = 29;
          #100
          D = 234;
          #100
          D = 115;
          #100
          D = 255;
          #100
          D = 168;
          #100
          D = 63;
          #100
          D = 102;
        end

      initial
        begin
          #1000;
          $stop;
        end

      initial
        begin
          $dumpfile("dump.vcd");
          $dumpvars(0);
        end

    endmodule
    ```
    ### design.cv
    ```
    // Code your design here
    module all_zero_one(D, Zero, One);
      input [7:0] D;
      output Zero, One;
      reg Zero, One, ZH, ZL, OH,OL;

      always@(D)
        begin
          check_tsk(D[7:4], ZH, OH);
          check_tsk(D[3:0], ZL, OL);
          Zero = ZH & ZL;
          One = OH& OL;
        end


      task check_tsk;
        input [3:0] I;
        output Z,O;

        {Z,O} = {~|I, &I};
      endtask


    endmodule
    ```