# How to use the AXI Master bus?

**Use an example to explain**
>m_axi is used to implement the AXI4 interface (high performance bus)
>Array or pointer/reference arguments
>Single data transfer or burst mode data transfer
>memcpy or for-loop
>For-loop
>* Pipeline the loop
>* Access in increasing order
>* Do not place access inside a conditional statement
>* For nested loop, do not flatten loops

**Parameter**
>1. **depth:** is the data size which you want to transfer
>2. **Port:** Specifies the name of the function argument, function return, or global variable which the INTERFACE pragma applies to
>3. **offset:** Controls the address offset in AXI4-Lite (s_axilite) and AXI4 (m_axi) interfaces
>4. **bundle:** Groups function arguments into AXI interface ports. By default, Vivado HLS groups all function arguments specified as an AXI4-Lite (s_axilite) interface into a single AXI4-Lite port
* **The in/output port must be a pointer/reference or array**

#include <iostream>
#include <stdint.h>
#include <ap_axi_sdata.h>

typedef unsigned int uint32_t;
using namespace std;

void AXI_Master_test(volatile uint32_t* DataIn,  volatile uint32_t* DataOut){
#pragma HLS INTERFACE m_axi depth=1024 port=DataIn offset=slave bundle=gmem0
#pragma HLS INTERFACE m_axi depth=1024 port=DataOut offset=slave bundle=gmem1
#pragma HLS INTERFACE s_axilite port=return
    for(int i = 0; i < 1024; ++i){
        DataOut[i] = DataIn[i];
    }


}

## Run the tcl file

open_project hls_AXI_Master_test_prj -reset
add_files  src/AXI_Master_test.cpp
add_files -tb src/AXI_Master_test.cpp
set_top AXI_Master_test
open_solution "solution0" -reset
set_part {xc7z020clg484-1}
create_clock -period 5 -name default
csim_design 
csynth_design 
cosim_design 
export_design -rtl verilog -format ip_catalog
close_project

## Create a project of vivado design suite