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# System prepended metadata

title: Xilinx SHA256 (include Vivado Suite block design flow)

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# Xilinx SHA256 (include Vivado Suite block design flow)

Use SHA256 with vivado2016.4 and SDK

## HLS Part
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Create a new HLS project
![](https://i.imgur.com/2gZUWTr.png)
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Add these four files and set sha256.c as top function 
The files should in Research-master.zip @Secure Boot Google Drive
![](https://i.imgur.com/qcEHbhg.png)
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Add sha256_tb.c as testbench file
![](https://i.imgur.com/jQj37fc.png)
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Select Zedboard
![](https://i.imgur.com/BEIvKN2.png)
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Run C simulation
![](https://i.imgur.com/z8YX7kq.png)
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![](https://i.imgur.com/KrQdOBn.png)
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Simulation result
![](https://i.imgur.com/mqwXPp5.png)
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Run C synthesis
![](https://i.imgur.com/er1bS7L.png)
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Synthesis result
![](https://i.imgur.com/U4bDoNu.png)
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Run C/RTL cosimulation
![](https://i.imgur.com/3ZtKAqW.png)
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![](https://i.imgur.com/yFJAt00.png)
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Simulation result
![](https://i.imgur.com/0r9lxFK.png)
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Export RTL
![](https://i.imgur.com/FvqZ6KH.png)
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![](https://i.imgur.com/zZd8nn7.png)
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The driver files are here
![](https://i.imgur.com/MrsFnDy.png)

## PL Part
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Add the RTL into our design and click "Run Connection Automation"
![](https://i.imgur.com/jKJ200O.png)
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Design diagram
![](https://i.imgur.com/GcbO4Vs.png)
Create HDL wrapper > Generate Bitstream > Export Hardware > Launch SDK

## SDK Part
Create a new project and in its src folder add these files from
https://github.com/bigbrett/wssha256vivado/tree/master/sha256test.sdk/sha256-test/src

![](https://i.imgur.com/Qvi8jUy.png)

## Result
This SHA256 seems correct when the size of input data is not larger than 256bytes (2048bits)
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Input data size is 256 byte
![](https://i.imgur.com/TDIpDt8.png)

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Input data size is 257 byte(wrong result)
![](https://i.imgur.com/ECDkH9U.png)






## Reference Website

https://drive.google.com/drive/u/1/folders/0ALkSJ_VWnyngUk9PVA

https://github.com/bigbrett/wssha256vivado/tree/master/sha256test.sdk/sha256-test/src

