# Xilinx SHA256 (include Vivado Suite block design flow)

Use SHA256 with vivado2016.4 and SDK

## HLS Part
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Create a new HLS project
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Add these four files and set sha256.c as top function
The files should in Research-master.zip @Secure Boot Google Drive
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Add sha256_tb.c as testbench file
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Select Zedboard
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Run C simulation
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Simulation result
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Run C synthesis
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Synthesis result
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Run C/RTL cosimulation
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Simulation result
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Export RTL
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The driver files are here

## PL Part
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Add the RTL into our design and click "Run Connection Automation"
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Design diagram
Create HDL wrapper > Generate Bitstream > Export Hardware > Launch SDK

## SDK Part
Create a new project and in its src folder add these files from
https://github.com/bigbrett/wssha256vivado/tree/master/sha256test.sdk/sha256-test/src


## Result
This SHA256 seems correct when the size of input data is not larger than 256bytes (2048bits)
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Input data size is 256 byte

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Input data size is 257 byte(wrong result)

## Reference Website

https://drive.google.com/drive/u/1/folders/0ALkSJ_VWnyngUk9PVA

https://github.com/bigbrett/wssha256vivado/tree/master/sha256test.sdk/sha256-test/src