# 文緯交接指引
編輯者: 石文緯
## 實驗
### 資料夾結構
WenWei --- top file
-- Thesis
-- Slides
-- Implementation
--- Detector
--- RecoverySimulation
--- SkipInstruction
-- References
### 在Implementation資料夾中有每個project 會用到的source, simulation, constraint files，依照vivado的開發流程即可重現。
### 簡易Vivado開發流程
* New 一個新的project出來，選擇開發版(Zedboard)。
* 加入所需的files，分別依照上面的constraints, design source, simulation sources加入，記得要按下Copy sources into project
* 全都加入之後，如果這個project是要run在板子上，直接按Generate Bitstream
### 開發技巧
* Run在FPGA時，如果需要使用到ILA，可以在synthesis之後，按圖示裡的Set Up Debug，將所需要觀察的signal往右邊拖曳，
選擇capture control，可以讓後面debug更容易。
將capture mode設定成basic，才能讓我們自由設定甚麼時候要capture。
Trigger setup設定reset後才開始作動。
因為我們必須要去capture每個cycle的值，但clock無法被capture，因此我們需要一個跟clock同步的counter來輔助，將capture設置成每個counter改變時已以及reset後才開始capture。
* 如果你發現開發的時候，vivado會去優化你想要的電路，可以在你想要的邏輯前面新增(\*dont_touch = "true"\*)，vivado就會避免優化掉所設計的電路邏輯，以我的work為例，我想要產生一個反向的delay chain，tool會認為你只是要反向而已，而幫你優化，因此我們需要特殊語法讓他避開。
* 指定想要的邏輯，FPGA的LUT通常只是用查表的方式實現你想要的邏輯，但如果你需要取用某個特別的邏輯，需要額外寫個module，直接取用某個特定邏輯。
* 設定constraint，由於我們想要真正跑在FPGA上面，top module的接腳都必須是有意義，因此我們必須讓他實現在開發版上的某個接腳，top module的in/output越多，所需的FPGA資源也會越多，使用時，必須先決定要使用的port，然後設定特定的電壓值。
底下為Zedboard可以使用的GPIO以及會需要設定的電壓值。
```
# ----------------------------------------------------------------------------
# _____
# / \
# /____ \____
# / \===\ \==/
# /___\===\___\/ AVNET Design Resource Center
# \======/ www.em.avnet.com/drc
# \====/
# ----------------------------------------------------------------------------
#
# Created With Avnet UCF Generator V0.4.0
# Date: Saturday, June 30, 2012
# Time: 12:18:55 AM
#
# This design is the property of Avnet. Publication of this
# design is not authorized without written consent from Avnet.
#
# Please direct any questions to:
# Avnet Centralized Technical Support
# Centralized-Support@avnet.com
# 1-800-422-9023
#
# Disclaimer:
# Avnet, Inc. makes no warranty for the use of this code or design.
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
# any errors, which may appear in this code, nor does it make a commitment
# to update the information contained herein. Avnet, Inc specifically
# disclaims any implied warranties of fitness for a particular purpose.
# Copyright(c) 2012 Avnet, Inc.
# All rights reserved.
#
# ----------------------------------------------------------------------------
#
# Notes:
#
# 10 August 2012
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
# By default, Vadj is expected to be set to 1.8V but if a different
# voltage is used for a particular design, then the corresponding IO
# standard within this UCF should also be updated to reflect the actual
# Vadj jumper selection.
#
# ----------------------------------------------------------------------------
# Bank 13, Vcco = 3.3V
NET AC-ADR0 LOC = AB1 | IOSTANDARD=LVCMOS33; # "AC-ADR0"
NET AC-ADR1 LOC = Y5 | IOSTANDARD=LVCMOS33; # "AC-ADR1"
NET AC-GPIO0 LOC = Y8 | IOSTANDARD=LVCMOS33; # "AC-GPIO0"
NET AC-GPIO1 LOC = AA7 | IOSTANDARD=LVCMOS33; # "AC-GPIO1"
NET AC-GPIO2 LOC = AA6 | IOSTANDARD=LVCMOS33; # "AC-GPIO2"
NET AC-GPIO3 LOC = Y6 | IOSTANDARD=LVCMOS33; # "AC-GPIO3"
NET AC-MCLK LOC = AB2 | IOSTANDARD=LVCMOS33; # "AC-MCLK"
NET AC-SCK LOC = AB4 | IOSTANDARD=LVCMOS33; # "AC-SCK"
NET AC-SDA LOC = AB5 | IOSTANDARD=LVCMOS33; # "AC-SDA"
NET FMC-SCL LOC = R7 | IOSTANDARD=LVCMOS33; # "FMC-SCL"
NET FMC-SDA LOC = U7 | IOSTANDARD=LVCMOS33; # "FMC-SDA"
NET GCLK LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK"
NET JA1 LOC = Y11 | IOSTANDARD=LVCMOS33; # "JA1"
NET JA10 LOC = AA8 | IOSTANDARD=LVCMOS33; # "JA10"
NET JA2 LOC = AA11 | IOSTANDARD=LVCMOS33; # "JA2"
NET JA3 LOC = Y10 | IOSTANDARD=LVCMOS33; # "JA3"
NET JA4 LOC = AA9 | IOSTANDARD=LVCMOS33; # "JA4"
NET JA7 LOC = AB11 | IOSTANDARD=LVCMOS33; # "JA7"
NET JA8 LOC = AB10 | IOSTANDARD=LVCMOS33; # "JA8"
NET JA9 LOC = AB9 | IOSTANDARD=LVCMOS33; # "JA9"
NET JB1 LOC = W12 | IOSTANDARD=LVCMOS33; # "JB1"
NET JB10 LOC = V8 | IOSTANDARD=LVCMOS33; # "JB10"
NET JB2 LOC = W11 | IOSTANDARD=LVCMOS33; # "JB2"
NET JB3 LOC = V10 | IOSTANDARD=LVCMOS33; # "JB3"
NET JB4 LOC = W8 | IOSTANDARD=LVCMOS33; # "JB4"
NET JB7 LOC = V12 | IOSTANDARD=LVCMOS33; # "JB7"
NET JB8 LOC = W10 | IOSTANDARD=LVCMOS33; # "JB8"
NET JB9 LOC = V9 | IOSTANDARD=LVCMOS33; # "JB9"
NET JC1_N LOC = AB6 | IOSTANDARD=LVCMOS33; # "JC1_N"
NET JC1_P LOC = AB7 | IOSTANDARD=LVCMOS33; # "JC1_P"
NET JC2_N LOC = AA4 | IOSTANDARD=LVCMOS33; # "JC2_N"
NET JC2_P LOC = Y4 | IOSTANDARD=LVCMOS33; # "JC2_P"
NET JC3_N LOC = T6 | IOSTANDARD=LVCMOS33; # "JC3_N"
NET JC3_P LOC = R6 | IOSTANDARD=LVCMOS33; # "JC3_P"
NET JC4_N LOC = U4 | IOSTANDARD=LVCMOS33; # "JC4_N"
NET JC4_P LOC = T4 | IOSTANDARD=LVCMOS33; # "JC4_P"
NET JD1_N LOC = W7 | IOSTANDARD=LVCMOS33; # "JD1_N"
NET JD1_P LOC = V7 | IOSTANDARD=LVCMOS33; # "JD1_P"
NET JD2_N LOC = V4 | IOSTANDARD=LVCMOS33; # "JD2_N"
NET JD2_P LOC = V5 | IOSTANDARD=LVCMOS33; # "JD2_P"
NET JD3_N LOC = W5 | IOSTANDARD=LVCMOS33; # "JD3_N"
NET JD3_P LOC = W6 | IOSTANDARD=LVCMOS33; # "JD3_P"
NET JD4_N LOC = U5 | IOSTANDARD=LVCMOS33; # "JD4_N"
NET JD4_P LOC = U6 | IOSTANDARD=LVCMOS33; # "JD4_P"
NET OLED-DC LOC = U10 | IOSTANDARD=LVCMOS33; # "OLED-DC"
NET OLED-RES LOC = U9 | IOSTANDARD=LVCMOS33; # "OLED-RES"
NET OLED-SCLK LOC = AB12 | IOSTANDARD=LVCMOS33; # "OLED-SCLK"
NET OLED-SDIN LOC = AA12 | IOSTANDARD=LVCMOS33; # "OLED-SDIN"
NET OLED-VBAT LOC = U11 | IOSTANDARD=LVCMOS33; # "OLED-VBAT"
NET OLED-VDD LOC = U12 | IOSTANDARD=LVCMOS33; # "OLED-VDD"
# Bank 33, Vcco = 3.3V
NET FMC-PRSNT LOC = AB14 | IOSTANDARD=LVCMOS33; # "FMC-PRSNT"
NET HD-CLK LOC = W18 | IOSTANDARD=LVCMOS33; # "HD-CLK"
NET HD-D0 LOC = Y13 | IOSTANDARD=LVCMOS33; # "HD-D0"
NET HD-D1 LOC = AA13 | IOSTANDARD=LVCMOS33; # "HD-D1"
NET HD-D10 LOC = W13 | IOSTANDARD=LVCMOS33; # "HD-D10"
NET HD-D11 LOC = W15 | IOSTANDARD=LVCMOS33; # "HD-D11"
NET HD-D12 LOC = V15 | IOSTANDARD=LVCMOS33; # "HD-D12"
NET HD-D13 LOC = U17 | IOSTANDARD=LVCMOS33; # "HD-D13"
NET HD-D14 LOC = V14 | IOSTANDARD=LVCMOS33; # "HD-D14"
NET HD-D15 LOC = V13 | IOSTANDARD=LVCMOS33; # "HD-D15"
NET HD-D2 LOC = AA14 | IOSTANDARD=LVCMOS33; # "HD-D2"
NET HD-D3 LOC = Y14 | IOSTANDARD=LVCMOS33; # "HD-D3"
NET HD-D4 LOC = AB15 | IOSTANDARD=LVCMOS33; # "HD-D4"
NET HD-D5 LOC = AB16 | IOSTANDARD=LVCMOS33; # "HD-D5"
NET HD-D6 LOC = AA16 | IOSTANDARD=LVCMOS33; # "HD-D6"
NET HD-D7 LOC = AB17 | IOSTANDARD=LVCMOS33; # "HD-D7"
NET HD-D8 LOC = AA17 | IOSTANDARD=LVCMOS33; # "HD-D8"
NET HD-D9 LOC = Y15 | IOSTANDARD=LVCMOS33; # "HD-D9"
NET HD-DE LOC = U16 | IOSTANDARD=LVCMOS33; # "HD-DE"
NET HD-HSYNC LOC = V17 | IOSTANDARD=LVCMOS33; # "HD-HSYNC"
NET HD-INT LOC = W16 | IOSTANDARD=LVCMOS33; # "HD-INT"
NET HD-SCL LOC = AA18 | IOSTANDARD=LVCMOS33; # "HD-SCL"
NET HD-SDA LOC = Y16 | IOSTANDARD=LVCMOS33; # "HD-SDA"
NET HD-SPDIF LOC = U15 | IOSTANDARD=LVCMOS33; # "HD-SPDIF"
NET HD-SPDIFO LOC = Y18 | IOSTANDARD=LVCMOS33; # "HD-SPDIFO"
NET HD-VSYNC LOC = W17 | IOSTANDARD=LVCMOS33; # "HD-VSYNC"
NET LD0 LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET LD1 LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1"
NET LD2 LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2"
NET LD3 LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3"
NET LD4 LOC = V22 | IOSTANDARD=LVCMOS33; # "LD4"
NET LD5 LOC = W22 | IOSTANDARD=LVCMOS33; # "LD5"
NET LD6 LOC = U19 | IOSTANDARD=LVCMOS33; # "LD6"
NET LD7 LOC = U14 | IOSTANDARD=LVCMOS33; # "LD7"
NET NetIC16_W20 LOC = W20 | IOSTANDARD=LVCMOS33; # "NetIC16_W20"
NET NetIC16_W21 LOC = W21 | IOSTANDARD=LVCMOS33; # "NetIC16_W21"
NET VGA-B1 LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1"
NET VGA-B2 LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2"
NET VGA-B3 LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3"
NET VGA-B4 LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4"
NET VGA-G1 LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1"
NET VGA-G2 LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2"
NET VGA-G3 LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3"
NET VGA-G4 LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4"
NET VGA-HS LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS"
NET VGA-R1 LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1"
NET VGA-R2 LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2"
NET VGA-R3 LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3"
NET VGA-R4 LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4"
NET VGA-VS LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS"
# Bank 34, Vcco = Vadj
NET BTNC LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC"
NET BTND LOC = R16 | IOSTANDARD=LVCMOS18; # "BTND"
NET BTNL LOC = N15 | IOSTANDARD=LVCMOS18; # "BTNL"
NET BTNR LOC = R18 | IOSTANDARD=LVCMOS18; # "BTNR"
NET BTNU LOC = T18 | IOSTANDARD=LVCMOS18; # "BTNU"
NET FMC-CLK0_N LOC = L19 | IOSTANDARD=LVCMOS18; # "FMC-CLK0_N"
NET FMC-CLK0_P LOC = L18 | IOSTANDARD=LVCMOS18; # "FMC-CLK0_P"
NET FMC-LA00_CC_N LOC = M20 | IOSTANDARD=LVCMOS18; # "FMC-LA00_CC_N"
NET FMC-LA00_CC_P LOC = M19 | IOSTANDARD=LVCMOS18; # "FMC-LA00_CC_P"
NET FMC-LA01_CC_N LOC = N20 | IOSTANDARD=LVCMOS18; # "FMC-LA01_CC_N"
NET FMC-LA01_CC_P LOC = N19 | IOSTANDARD=LVCMOS18; # "FMC-LA01_CC_P"
NET FMC-LA02_N LOC = P18 | IOSTANDARD=LVCMOS18; # "FMC-LA02_N"
NET FMC-LA02_P LOC = P17 | IOSTANDARD=LVCMOS18; # "FMC-LA02_P"
NET FMC-LA03_N LOC = P22 | IOSTANDARD=LVCMOS18; # "FMC-LA03_N"
NET FMC-LA03_P LOC = N22 | IOSTANDARD=LVCMOS18; # "FMC-LA03_P"
NET FMC-LA04_N LOC = M22 | IOSTANDARD=LVCMOS18; # "FMC-LA04_N"
NET FMC-LA04_P LOC = M21 | IOSTANDARD=LVCMOS18; # "FMC-LA04_P"
NET FMC-LA05_N LOC = K18 | IOSTANDARD=LVCMOS18; # "FMC-LA05_N"
NET FMC-LA05_P LOC = J18 | IOSTANDARD=LVCMOS18; # "FMC-LA05_P"
NET FMC-LA06_N LOC = L22 | IOSTANDARD=LVCMOS18; # "FMC-LA06_N"
NET FMC-LA06_P LOC = L21 | IOSTANDARD=LVCMOS18; # "FMC-LA06_P"
NET FMC-LA07_N LOC = T17 | IOSTANDARD=LVCMOS18; # "FMC-LA07_N"
NET FMC-LA07_P LOC = T16 | IOSTANDARD=LVCMOS18; # "FMC-LA07_P"
NET FMC-LA08_N LOC = J22 | IOSTANDARD=LVCMOS18; # "FMC-LA08_N"
NET FMC-LA08_P LOC = J21 | IOSTANDARD=LVCMOS18; # "FMC-LA08_P"
NET FMC-LA09_N LOC = R21 | IOSTANDARD=LVCMOS18; # "FMC-LA09_N"
NET FMC-LA09_P LOC = R20 | IOSTANDARD=LVCMOS18; # "FMC-LA09_P"
NET FMC-LA10_N LOC = T19 | IOSTANDARD=LVCMOS18; # "FMC-LA10_N"
NET FMC-LA10_P LOC = R19 | IOSTANDARD=LVCMOS18; # "FMC-LA10_P"
NET FMC-LA11_N LOC = N18 | IOSTANDARD=LVCMOS18; # "FMC-LA11_N"
NET FMC-LA11_P LOC = N17 | IOSTANDARD=LVCMOS18; # "FMC-LA11_P"
NET FMC-LA12_N LOC = P21 | IOSTANDARD=LVCMOS18; # "FMC-LA12_N"
NET FMC-LA12_P LOC = P20 | IOSTANDARD=LVCMOS18; # "FMC-LA12_P"
NET FMC-LA13_N LOC = M17 | IOSTANDARD=LVCMOS18; # "FMC-LA13_N"
NET FMC-LA13_P LOC = L17 | IOSTANDARD=LVCMOS18; # "FMC-LA13_P"
NET FMC-LA14_N LOC = K20 | IOSTANDARD=LVCMOS18; # "FMC-LA14_N"
NET FMC-LA14_P LOC = K19 | IOSTANDARD=LVCMOS18; # "FMC-LA14_P"
NET FMC-LA15_N LOC = J17 | IOSTANDARD=LVCMOS18; # "FMC-LA15_N"
NET FMC-LA15_P LOC = J16 | IOSTANDARD=LVCMOS18; # "FMC-LA15_P"
NET FMC-LA16_N LOC = K21 | IOSTANDARD=LVCMOS18; # "FMC-LA16_N"
NET FMC-LA16_P LOC = J20 | IOSTANDARD=LVCMOS18; # "FMC-LA16_P"
NET OTG-VBUSOC LOC = L16 | IOSTANDARD=LVCMOS18; # "OTG-VBUSOC"
NET PUDC_B LOC = K16 | IOSTANDARD=LVCMOS18; # "PUDC_B"
NET XADC-GIO0 LOC = H15; # "XADC-GIO0"
NET XADC-GIO1 LOC = R15; # "XADC-GIO1"
NET XADC-GIO2 LOC = K15; # "XADC-GIO2"
NET XADC-GIO3 LOC = J15; # "XADC-GIO3"
# Bank 35, Vcco = Vadj
NET FMC-CLK1_N LOC = C19 | IOSTANDARD=LVCMOS18; # "FMC-CLK1_N"
NET FMC-CLK1_P LOC = D18 | IOSTANDARD=LVCMOS18; # "FMC-CLK1_P"
NET FMC-LA17_CC_N LOC = B20 | IOSTANDARD=LVCMOS18; # "FMC-LA17_CC_N"
NET FMC-LA17_CC_P LOC = B19 | IOSTANDARD=LVCMOS18; # "FMC-LA17_CC_P"
NET FMC-LA18_CC_N LOC = C20 | IOSTANDARD=LVCMOS18; # "FMC-LA18_CC_N"
NET FMC-LA18_CC_P LOC = D20 | IOSTANDARD=LVCMOS18; # "FMC-LA18_CC_P"
NET FMC-LA19_N LOC = G16 | IOSTANDARD=LVCMOS18; # "FMC-LA19_N"
NET FMC-LA19_P LOC = G15 | IOSTANDARD=LVCMOS18; # "FMC-LA19_P"
NET FMC-LA20_N LOC = G21 | IOSTANDARD=LVCMOS18; # "FMC-LA20_N"
NET FMC-LA20_P LOC = G20 | IOSTANDARD=LVCMOS18; # "FMC-LA20_P"
NET FMC-LA21_N LOC = E20 | IOSTANDARD=LVCMOS18; # "FMC-LA21_N"
NET FMC-LA21_P LOC = E19 | IOSTANDARD=LVCMOS18; # "FMC-LA21_P"
NET FMC-LA22_N LOC = F19 | IOSTANDARD=LVCMOS18; # "FMC-LA22_N"
NET FMC-LA22_P LOC = G19 | IOSTANDARD=LVCMOS18; # "FMC-LA22_P"
NET FMC-LA23_N LOC = D15 | IOSTANDARD=LVCMOS18; # "FMC-LA23_N"
NET FMC-LA23_P LOC = E15 | IOSTANDARD=LVCMOS18; # "FMC-LA23_P"
NET FMC-LA24_N LOC = A19 | IOSTANDARD=LVCMOS18; # "FMC-LA24_N"
NET FMC-LA24_P LOC = A18 | IOSTANDARD=LVCMOS18; # "FMC-LA24_P"
NET FMC-LA25_N LOC = C22 | IOSTANDARD=LVCMOS18; # "FMC-LA25_N"
NET FMC-LA25_P LOC = D22 | IOSTANDARD=LVCMOS18; # "FMC-LA25_P"
NET FMC-LA26_N LOC = E18 | IOSTANDARD=LVCMOS18; # "FMC-LA26_N"
NET FMC-LA26_P LOC = F18 | IOSTANDARD=LVCMOS18; # "FMC-LA26_P"
NET FMC-LA27_N LOC = D21 | IOSTANDARD=LVCMOS18; # "FMC-LA27_N"
NET FMC-LA27_P LOC = E21 | IOSTANDARD=LVCMOS18; # "FMC-LA27_P"
NET FMC-LA28_N LOC = A17 | IOSTANDARD=LVCMOS18; # "FMC-LA28_N"
NET FMC-LA28_P LOC = A16 | IOSTANDARD=LVCMOS18; # "FMC-LA28_P"
NET FMC-LA29_N LOC = C18 | IOSTANDARD=LVCMOS18; # "FMC-LA29_N"
NET FMC-LA29_P LOC = C17 | IOSTANDARD=LVCMOS18; # "FMC-LA29_P"
NET FMC-LA30_N LOC = B15 | IOSTANDARD=LVCMOS18; # "FMC-LA30_N"
NET FMC-LA30_P LOC = C15 | IOSTANDARD=LVCMOS18; # "FMC-LA30_P"
NET FMC-LA31_N LOC = B17 | IOSTANDARD=LVCMOS18; # "FMC-LA31_N"
NET FMC-LA31_P LOC = B16 | IOSTANDARD=LVCMOS18; # "FMC-LA31_P"
NET FMC-LA32_N LOC = A22 | IOSTANDARD=LVCMOS18; # "FMC-LA32_N"
NET FMC-LA32_P LOC = A21 | IOSTANDARD=LVCMOS18; # "FMC-LA32_P"
NET FMC-LA33_N LOC = B22 | IOSTANDARD=LVCMOS18; # "FMC-LA33_N"
NET FMC-LA33_P LOC = B21 | IOSTANDARD=LVCMOS18; # "FMC-LA33_P"
NET OTG-RESETN LOC = G17 | IOSTANDARD=LVCMOS18; # "OTG-RESETN"
NET SW0 LOC = F22 | IOSTANDARD=LVCMOS18; # "SW0"
NET SW1 LOC = G22 | IOSTANDARD=LVCMOS18; # "SW1"
NET SW2 LOC = H22 | IOSTANDARD=LVCMOS18; # "SW2"
NET SW3 LOC = F21 | IOSTANDARD=LVCMOS18; # "SW3"
NET SW4 LOC = H19 | IOSTANDARD=LVCMOS18; # "SW4"
NET SW5 LOC = H18 | IOSTANDARD=LVCMOS18; # "SW5"
NET SW6 LOC = H17 | IOSTANDARD=LVCMOS18; # "SW6"
NET SW7 LOC = M15 | IOSTANDARD=LVCMOS18; # "SW7"
NET XADC-AD0N-R LOC = E16; # "XADC-AD0N-R"
NET XADC-AD0P-R LOC = F16; # "XADC-AD0P-R"
NET XADC-AD8N-R LOC = D17; # "XADC-AD8N-R"
NET XADC-AD8P-R LOC = D16; # "XADC-AD8P-R"
```
* 如何使用FPGA裡面的Block RAM(BRAM) implement，我透過使用(\*ram_style = "block"\*)來實現，切記你所要implement的那個reg一定是要sequential circuit，也就是他的read/write都必須要是跟著clock，tool才會使用BRAM做實現，要不然他就會以一般的LUT及Flip-Flop實現。
Sythesis完之後可以透過report utilization去確認是否使用BRAM做實現。
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