# Introduction of Computer Science<br>Ch5 & Ch6
NTNU 計算機概論

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###### tags: `NTNU` `CSIE` `必修` `Introduction of Computer Sciencce`

# Ch5. Computer Organization
## 5-1 Computer Hardware(3 subsystems)

## 5-2 CPU(Central Processing Unit)
The CPU processing unit performs operations on data.
- Arithmetic logic unit
- control unit
- **controls the operation** of CPU

- Machine Cycle(repeat)
- Fetch→decode→execute
- Registers
- fast storage locations that **hold data temporarily**
- Data registers
- Input data
- Output data
- Registers in Control Unit
- IR：Instruction registers
- PC：Program counter
### Moore's Law
Number of transistors on the wafer **multiply every 18 months**
- Extended application

1. *Computer computing speed* multiply every 18 months
2. *Storage capacity* multiply every 18 months
3. *Network speed* multiply every 18 months

## 5-3 Main Memory
### Memory Evolution
- SIMM (Single In-line Memory Modules)
- 30pin SIMM
- 70pin SIMM
- EDO DRAM (Extanded Data Out RAM)
- 168pin SDRAM
- RDRAM / DRDRAM (Direct Rambus DRAM)
- DDR SDRAM (Dual Data Rate SDRAM)
- DDR2
- DDR3
- DDR4

### Main Memory
#### Addresses
Because computers operate by storing numbers as *bit patterns*, the address itself is also represented as a *bit pattern*

Memory addresses are defined using **unsigned binary integers**

- 16 bits (2^16^=65535=64K Bytes)

### Measuring Memory Capacity

| Unit | bytes | Approximation |
| --------- | ----- | ------------- |
| Kilobyte | 2^10^ | 10^3^ |
| Megabyte | 2^20^ | 10^6^ |
| Gigabyte | 2^30^ | 10^9^ |
| Terabyte | 2^40^ | 10^12^ |
| Petabyte | 2^50^ | 10^15^ |
| Exabyte | 2^60^ | 10^18^ |
| Zetabyte | 2^70^ | 10^21^ |
| Yottabyte | 2^80^ | 10^24^ |

| | | |
| --- | -------- | ------- |
| | -------- | ------- |
| $d$ | deci | 10^-1^ |
| $c$ | centi | 10^-2^ |
| $m$ | milli | 10^-3^ |
| $μ$ | micro | 10^-6^ |
| $n$ | nano | 10^-9^ |
| $p$ | pico | 10^-12^ |
| $f$ | femto | 10^-15^ |
| $a$ | atto | 10^-18^ |
| $z$ | zepto | 10^-21^ |
| $y$ | yocto | 10^-24^ |

### Memory hierarchy
| Registers | Cache Memory | Main Memory |
| ----------- | ------------ | ----------- |
| high-speed | medium-speed | low-speed |
| More costly | | Less costly |
| | SRAM | DRAM |
#### Memory Type (Both can be accessed randomly)
- RAM (Random Access Memory)
<br>**Volatile**：the data is erased if the system is powered down.
- SRAM (Static RAM)
- flip-flop gates
- no need to be refreshed
- for *Catch memory*
- DRAM (Dynamic RAM)
- capacitors
- need to be refreshed periodically
- for *Main memory*
- ROM (Read Only Memory)
<br>**Nonvolatile**
<br>The contents of ROM com from the manufacturer.
<br>Users are only allowed to read from it,but not write to it.
<br>For *Booting program*
- PROM (Programmable ROM)
- Only write one time
- EPROM (erasable programmable ROM)
- Use ultraviolet light to erase data
- EEPROM (electronically erasable programmable ROM )
- Can be erased using electronic impulses
#### Cache Memory
- High-speed memory to **hold the most recent data and instructions** that have been loaded by the CPU.
- Cache is located directly on the CPU or between the CPU and RAM, making it faster than normal RAM.
- CPU-resident cache is called Level-1 cache. External cache is called is called Level-2 cache.
- 現在L2、L3均已CPU-resident
- Contains a copy of a portion of main memory.
- When the CPU needs to access a word in main memory, CPU checks the cache.
- [cache_wikipedia](https://zh.wikipedia.org/wiki/%E7%BC%93%E5%AD%98)
### 80/20 Rule Pareto principle
- Most computers typically spend 80% of the time accessing only 20% of the data.
### Benford's First Digit Law
1983 Frank Benford find ：data start with '1' appear probability is 30.1%, '2' is 17.6%, decreasing in sequence, '9' is 4.6%
## Ch5-4 Input/Output Subsystem
- The input/output subsystem is a collection of devices that allows a computer to communicate with the outside world.
- These devices are either non-storage devices or storage devices.
- RPM：Revolution per minute
- Non-storage Devices:
- Keyboard
- Monitor
- Printer
- Storage Devices:
+ Magnetic(磁性的) storage devices
+ Hard Disk
+ Data access
+ Random access
+ one sector a time
+ Access time
+ Seek time：the time move recording head
+ Rotational speed：the time move to a sector
+ Transfer time：Transfer rate, a sector from hard disk to main memory.
+ Optical(光學的) storage devices
+ DVD (Digital Versatile Disk)
- single/double side,single/double layer
- DVD has roughly 50,000 tracks and 40 sectors(2KB) per track.
- DVD uses **MPEG** (Moving Picture Expert Group) for compression
- A single-side single-layer DVD
- 133 minutes of video at high resolution
- DVD-Audio：sampling rate 44.1-192kHz, 16/20/24 bits per sample
- Ultra HD Blu-ray capacity 100GB support 4KUHD

## 5-5 Subsystem Nterconnection
### Connecting CPU and memory using three buses
A data bus, an address bus, and a control bus connect the CPU and memory.
### Connecting I/O devices to the buses
Serial controller used to connect slower devices such as the keyboard and mouse to a computer.

| USB | Transfer rate |
| ------ |:------------- |
| USB 1.0 | 1.5M bits/s |
| USB 2.0 | 480M bits/s |
| USB 3.0 | 4.8G bits/s |

### 2 Methods for addressing I/O
- Isolated I/O Addressing
- The instructions used to read/write memory are different from the instructions used to read/write input/output device.
- Advantages
- I/O不佔Memory→Memory真正可用空間較大
- 有專屬輸出入指令，程是容易區別I/O動作
- I/O空間較小，I/O解碼定址較簡單快速
- Disadvantages
- CPU中必須有一隻接角，以區別是要存取I/O或Memory
- 程式較無效率，在I/O埠上只能做簡單IN/OUT動作，不能 處裡，必須將資料讀進memory後，再做處裡
- Memory-Mapped I/O Addressing
- CPU does not have separate instructions for transferring data from memory or input/output device.
- Advantages
- 在記憶體上可做的運算，在I/O上也可以，故寫的程式也較有效率
- CPU不必有區別M/IO的接腳
- Disadvantages
- 無IN/OUT指令，程式中不易區別何者在進行I/O動作
- 解碼較慢
- 全部可用的記憶體減少
## 5-6 Program Execution
### Three Methods
- Programmed I/O (又稱Polled I/O)
- CPU每隔一段時間檢查I/O設備是否需要服務。
- 方法很簡單，但最沒有效率。
- CPU time is wasted in checking the status of the I/O device for each unit of data to be transferred.
- Interrupt-driven I/O
- 1.Issued I/O command :
- The CPU will notify the screen of the mode to be transmitted.<!--CPU會通知screen所要傳送的模式-->
- e.g. 7bits or 8bits，parity check?
- 2. The CPU does other work.
- If the device is already ready, it sends an interrupt signal to the CPU.<!--CPU就去做其他的工作，如果device已經ready，則發出interrupt訊號給CPU。-->
- 3. Then the CPU executes the interrupt service routine, which sends a word.<!--接著CPU執行interrupt service routine，此程式就會傳送一個word。-->
- 軟硬體設計較複雜，但較有效率。
- DMA connection to the general bus
- I/O設備透過DMA通到來直接存取記憶體→最複雜，但最有效率。
- 1. The CPU sets *the start address, control mode, number, etc.* of the Buffer.
- 2. After the DMA(Direct Memory access) is ready, send a Bus request to the CPU.
- 3. Disk transfers data to Buffer.
- 4. DMA pass to reply acknowledge confirmation signal
- 5. Buffer data is directly transferred to memory
<!-- 1. CPU設定Buffer的起始位址、控制模式、數量等。
- 2. DMA通到準備妥當後，向CPU發出Bus request
- 3. Disk傳資料到Buffer。
- 4. DMA通到回覆acknowledge確認訊號
- 5. Buffer中資料直接傳到memory中
-->
### CPU的指令集
|比較項目|複雜指令集(CISC)|精簡指令集(RISC)|
|------|---------------|--------------|
|全名|Complex Instruction Set Computer|Reduced Intruction Set Computer|
|指令長度|較長，而且不固定|較短，而且固定|
|指令數|較多(100-300)|較少(<100)|
|執行時間|較長|較短|
|程式設計|較容易|較困難|
|主要用途|桌機、伺服器|導航、交換器、路由器|
### Pipelining(管線化)
Modern computer use a technique called pipelining to improve the throughput(產能).

The idea is that if control unit can do two or three of these phases simultaneously, the next instruction can start before the previous one is finished.
### Parallel processing(平行處理)
A single computer with multiple control units, multiple arithmetic logic units and multiple memory units.
- SISD organization
- **S**ingle **I**nsturction-stream, **S**ingle **D**ata-stream
- Computer only have a control unit, a processing unit, and a memory unit。
- The instructions are executed sequentially and each instruction can access a data in the data-stream.<!--instruction依序地執行而且每個instruction可以存取data-stream中一個data。-->
- e.g. Normal PC、Navigator
- SIMD organization
- **S**ingle **I**nsturction-stream, **M**utiple **D**ata-stream
- Computer only has one control unit, multiple processing units, and multiple memory units.
- All processing units accept the same instructions from the control unit, but operate on different data-streams.<!--所有的processing unit接受來自control unit的相同指令，但是對不同的data-stream做運算。-->
     - A shattering processor that computes data from an array at the same time belongs to this class.<!-- 同時對一個陣列的資料做運算之震裂處理器就是屬於這類。-->
- e.g. ILLIAC IV、TMC CM-5、CRAY T3D、GPU
- MISD organization
- **M**utiple **I**nsturction-stream, **S**ingle **D**ata-stream
- The computer has **multiple instructions** belonging to **multiple different instruction-systems**, and performs operations on the **same data-stream**.<!--計算機有多個指令分別屬於多個不同的instruction-system，同時對同一個data-stream做運算-->
- The concept of MISD **has never been done**.<!--MISD的概念從未實做過。-->
- MIMD organization
- **M**utiple **I**nsturction-stream,**M**utiple **D**ata-stream
- Computer has mutiple instructions which belong to different instruction-stream,and operate on different data-streams.<!--所有的processing unit接受來自control unit的相同指令，但是對不同的data-stream做運算。-->
## 5-8 A Simple Computer
### Instruction Set
- Computer Instruction Consists
- Operation code
- Operand(s)
- The opcode specifies the type of operation to be performed on the operand(s).
- Each instruction consists of sixteen bits divvided into four 4-bits fields.
- The leftmost field contains the opcode and the other three fields contains the operand or address of operands.

# Ch6. Computer Networks
## 6-1 Overview

### 網路種類
| 網路種類 | 全名 | 涵蓋範圍 | 速度 | 通訊品質 | 連線設備 |
|:-------------:|:-------------------------------------:|:------------------------------:|:----:|:--------:|:-------------------------------- |
| LAN(區域網路) | **L**ocal **A**rea **N**etwork | 小<br>(大樓內、學校內) | 快 | 佳 | 電纜、光纖 |
| MAN(都會網路) | **M**etropolitan **A**rea **N**etwork | 中<br>(一個都市、多個區域網路) | 中 | 中 | |
| WAN(廣域網路) | **W**ide **A**rea **N**etwork | 廣<br> | 慢 | 差 | 電話線、海底電纜、微波、衛星通道 |
### TANet臺灣學術網路(Taiwan Academic Network)
[TANet臺灣學術網路](https://noc.tanet.edu.tw/)

[TANet_Wikipedia](https://zh.wikipedia.org/wiki/TANet)

NTNU IP：140.122
### Model and Protocol
A model is the specification set by a standards organization as a guideline for designing networks
是一種學理上的、抽象的規範，比較像指導方針 ex:ISO's OSI model in 1974
#### OSI Model(The Open System Interconnection)
1974 International Standard Organization

| No. | Layer | 中文 | Using |
| --- | ------------------ | -------------- | ----- |
| 7 | Application Layer | 應用層 |系統與使用者交談的介面|
| 6 | Presentation Layer | 表達層(展示層) | |
| 5 | Session Layer | 會議層 | |
| 4 | Transport Layer | 傳輸層 | |
| 3 | Network Layer | 網路層 | IP address |
| 2 | Data Link Layer | 資料連結層 | Mac address |
| 1 | Physical Layer | 實體層 | |

- 口訣：英打會輸入結石

#### TCP/IP Protocol Suite(**T**ranmission **C**ontrol **P**rotocol/**I**nternet **P**rotocol)

| No. | Layer | 中文 | Protocol |
| --- | ----------------- | ---------- | -------------------------- |
| 5 | Application Layer | 應用層 | FTP、SMTP、TELNET、HTTP... |
| 4 | Transport Layer | 傳輸層 | TCP、UDP |
| 3 | Network Layer | 網路層 | IP |
| 2 | Data Link Layer | 資料連結層 | |
| 1 | Physical Layer | 實體層 | |
## 6-2 Application Layer
### P2P (peer-to-peer paradigm)
### Client-server paradigm
### WWW(World Wide Web)

{%hackmd @sophie8909/csabb %}