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# System prepended metadata

title: VLSI 3
tags: [VLSI]

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---
title: VLSI 3
tags: VLSI
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# VLSI 3 - Behavior and Structural Model


## Models
1. Dataflow model(適合簡單組合邏輯)
    - Concurrent Signal Assignments
2. Behavior model（適合稍微複雜一點的）
    - sequential Assignments(signal + variable)
    - Inside Process Statements
3. Structural model（適合電路太大的話，可以拆成好幾個部分）
    - Netlist
## Statements
### Process Statement
#### If statement
- Includes Latch(記憶裝置)
##### Review
:::spoiler 點開看 Latch
![](https://i.imgur.com/FBiWVsY.png)
:::
:::spoiler 點開看 DFF
![](https://i.imgur.com/HidVnV6.png) 
:::
### Variable Assignment Statements

$\vdots$
好多的 Statements
自己去看講義啦ㄏ


## Notes for homework
Clock Cycle: 20ns = 50MHz
- 可能會有 reset 
    - 提到 reset 的 statement
        - wait
        - if
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