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title: VLSI 2
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# VLSI Computer-Aided Design for VLSI Design
NTNU VLSI 電腦輔助設計
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###### tags: `VLSI` `110-1` `CSIE` `選修` `NTNU`
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## Ch2. VHDL-Basic Elements and Dataflow
### Identifiers and Data Objects
#### Iderntifiers
#### Data Objects
- holds a value of a specified type
- created bt means of an object declaration

- Every data object belongs to one of the following four classes
1. Constant
- declaration
- simple example
- `constant BUS_WIDTH: INTER :=8;`
2. Varible
- declaration
- simple example
- `varibale FOUND, DOWN: BOOLEAN;`
3. Signal
- declaration
- simple example
```vhdl=
signal CLOCK: BIT;
signal DATA_BUS: BIT_VECTOR(0 to 7);
signal INIT_P: STD_LOGIC_VECTOR(7 downto 0);
```
4. File
### Data Types of VHDL
<!-- 縮起來好打 -->
1. Scalar Types
- Enumeration
- BOOLEAN (FALSE, TRUE)
- BIT ('0', '1')
- STD_LOGIC
- not default, need `STD_LOGIC_1164` package
- values
| value | explain | |
| ----- | --------------- | --- |
| 'U' | Un-Initialed | |
| 'X' | Forcing Unknown | |
| '0' | Forcing 0 | |
| '1' | Forcing 1 | |
| 'Z' | High Impedance | |
| 'W' | Week Unknown | |
| 'L' | Week Low | |
| 'H' | Week High | |
| '-' | Don't Care | |
- Integer
- range: (0, 15), 4 bits
- Physical
<font class="caption">不常用</font>
- Floating
<font class="caption">不常用,高階語言的 floating 是由硬體算出來的所以在硬體這邊這堂課先不討論。</font>
2. Composite Types
- Array
```vhdl=
type ADDRESS_WORD is arr
```

- BIT_VECTOR
- STRING
- STD_LOGIC_VECTOR
- Record
<font class="caption">不常用</font>
3. Access Types
4. File Types
<!-- 1015 大概講到 ARRAYhttps://moodle3.ntnu.edu.tw/ -->
- Difference between downto and to
- 沒聽清楚他說啥,但結論是建議用 downto
- 因為多數工程師用 downto,若你用 to 合併可能會出問題
### Operators and Attributes
The predefined operators in the language are classified into the following 6 categories:
1. Logical operators
2. Relational operators
3. Shift operators
4. Adding operators
5. Multiplying operators
6. Miscellaneous operators
### Dataflow Model
### Entity Declaration and Architecture Body
### Concurrent Signal Assignment
### Conditional Signal Assignment
### Selected Signal Assignment