---
title: VLSI 1
---
# VLSI Computer-Aided Design for VLSI Design
NTNU VLSI 電腦輔助設計

##### [Back to Note Overview](https://reurl.cc/XXeYaE)
##### [Back to VLSI Computer-Aided Design for VLSI Design](https://hackmd.io/@NTNUCSIE112/VLSI110-1)
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###### tags: `VLSI` `110-1` `CSIE` `選修` `NTNU`
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## Ch.01 Introduction to VLSI Design
[影片惡補](https://www.youtube.com/watch?v=P91wpwVGH6M&list=LL&index=6&ab_channel=%E7%A1%AC%E4%BB%B6%E8%8C%B6%E8%B0%88)
### Transistors and Circuit Fabrication
#### Semiconductor
- A **pure semiconductor** is actually an **insulator**.
- A typical example of semiconductor is **silicon**.
- By doping carefully controlled **impurities**, a semiconductor can become a **conductor**.
- Different types of semiconductor(They can complement each other into CMOS)
- **p-type** semiconductor
- doped with atoms having 3 valence electron(acceptors). The semiconductor therefore has holes.
- **n-type** semiconductor
- doped with atoms having 5 valence electrons (donors). The semiconductor therefore has free electrons.

| | p-type | n-type |
| ----------------- | ------------------------------------------------ | ------------------------------------------------ |
| doped with | acceptors(having 3 valence) | donors(having 5 valence) |
| semiconductor has | holes | free electrons |
| doped examples | With Boron | With Antimony |
| Picture |  |  |

:::info
The simplest semiconductor device is the diode.
> A diode allow the current in one direction (from p to n),
and block the current in the other direction
(from n to p).
:::spoiler The Process of a Diode.
> 1. After holes and free valence combine, a depletion layer(stable area) appears between p-type & n-type

> 2. If we connect positive electrode to p-type and negitive electrode to n-type, the depletion layer disappears :arrow_right: current flow.

> 3. On the other hand, if we connect positive electrode to n-type and negitive electrode to p-type, the depletion layer appears :arrow_right: current doesn't flow.
:::
#### MOS(Metal Oxide Semiconductor) Transistor

- The MOS transistor has **<font color="red">three</font>** terminals
- **gate**, **source** and **drain**
- The MOS transistor has two types
:::spoiler nMOS (n-channel MOS)
- 
- requires a logic value **1** on gate to be on
- the cross section of the nMOS
- The gate of the first MOS is made of metal. It is now made of polysilicon.
- L: Length of Channel（傳統上講製程 xx nm 指的部分）
- W: Width of Channel
- Operations of nMOS
- Source is connected to ground
- g=0 implies Vg is below a threshold
- In this case, the channel is p-type. It is off.
- g=1 implies Vg is above a threshold.
- The positive Vg attracts electrons to the channel, which then becomes n-type. The connection between drain and source is then established. The output=0V.
:::
:::spoiler pMOS (p-channel MOS)
- 
- requires a logic value **0** on gate to be on
:::
- The MOS transistor is basically a switch when used for digital circuit design. It can be on or off.
- When **on**, a current flow between source and drain.
- When **off**, no current flow between source and drain.
#### Transistor/Circuit Fabrication
<!-- 無腦複製中 我不知道在幹嘛 -->
##### Circuit fabrication steps (simplified)
1. The starting material for circuit fabrication is very high purity silicon. The material is grown as a single crystal ingot.
2. The crystal is then sawed to produce wafers.
3. The repeated copies of the circuit are then implementedon the wafer.
To implement repeated copies of a circuit on the wafer, a special resin (樹脂) called “photoresist (光阻劑)” is coated over the entire wafer.
Photoresist is a special resin similar in behavior to photography films that changes properties when exposed to light.
The photoresist-coated wafer is then irradiated to have the circuit diagram transcribed onto it. This process is also called “photo lithography(光微影)” process.
An irradiation device called the "stepper" is used to irradiate the wafer through the mask with ultraviolet (UV) light.
The photo mask is based on the layout of the circuit.

Therefore, it is essential to design a good layout (not
a circuit diagram) for chip fabrication.

5. Finally, we cut the wafer into dies, and then package.

### Complimentary MOS (CMOS) Circuits and Logic Gates
<!-- Start from slide 34 -->
- A CMOS circuit contains both nMOS and pMOS transistors, as shown below.
- 
- pMOS 接 VDD，nMOS 接地 :warning: 不可相反
<!-- 錯的就不放了避免搞混 -->
#### Basic Logic Fates
基礎的邏輯閘是 NAMD 和 NOR 不是 AND 和 NOR 的原因跟 nMOS、pMOS 有關
:::spoiler Basic
- NOT - The Most Easy CMOS circuit
- 
- In =1, M1 ON, M2 OFF
- In =0, M1 OFF, M2 ON
- NAND
- 
- 
- $V_A$=1, $V_B$=0, M1 ON, M2 OFF, M3 ON, M4 OFF Vout=1
- 
- NOR
- 
- 
- $V_A$=1, $V_B$=0, M1 ON, M2 OFF, M3 ON, M4 OFF Vout=0
- 
:::

:::spoiler Non-Basic
- AND = NOT + NAND
- 
- OR = NOT + NOR
- 
:::
### Digital Circuits
Logic gates can be used to implement digital circuits.
Some commonly used digital circuits are
1. Multiplexer
2. Latch
3. Flip flop (FF)
#### 1. Multiplexer

2 to 1 Multiplexer
 

| X | A | B | Y |
| --- | --- | --- | --- |
| 1 | X | 0 | 0 |
| 1 | X | 1 | 1 |
| 0 | 0 | X | 0 |
| 0 | 1 | X | 1 |

<!-- 1001 class end (slide 53)-->
#### 2. Latch
CLK: clock
- CLK = 1 -> D flows to Q
- CLK = 0 -> Q doesn't change

#### 3. Flip-Flop
##### **D-Type Flip-Flop (FF)**
> The D-type FF is able to hold data temporarily. We can only change the data stored by D-type FF at the **rising edge**.
The D-type FF is also called the <font color="red">register</font>.


<div style="display: inline-block;">
<img src="https://i.imgur.com/VW9uzj1.png">
<p style="text-align: right; color: grey;" >注：↑為0 to 1 的瞬間、↓為 1 to 0 的瞬間</p>
</div>

When CLK rises, D is copied to Q. At all other times, Q holds its value.

### VLSI Design Flow and Style
- Very-large-scale integration(VLSI)
- the process of creatig integrated circuits by combining thousands of transistor-based circuits into a single chip.
#### VLSI Costs
There are two types of costs considered in the VLSI design
1. NRE (Non-Recurring Engineering) Costs
跟產量無關的東西（e.g. 人事、設計成本、光罩板）
- Fixed cost to produce the design
- design effort
- design verification effort
- mask generation
- Influenced by the design complexity and designer productivity
- More pronounced for small volume products
2. Recurring Cost
- silicon processing
- also proportional to chip area
- assembly (packaging)
- test

#### VLSI Design Flow
The VLSI design process may be viewed as a five-stage process as shown below
- Specification
- Register Transfer Level (RTL) Design
- Gate Level Design
- Circuit Level Design
- Physical Design

#### RTL Level Design and Gate Level Design
A digital system is specified at the register transfer level
when it is specified by
1. A set of registers,
2. The operations over the data stored on the registers,
3. The control that supervises the operations.

The design rule check (DRC) also needs be enforced to
avoid possible fabrication failure.

- Width 過小→消失
- Spacing 過近→黏在一起
- Enclosure margin 太小 Metal Contact 可能打錯地方

#### Major VLSI Design Styles
4 major design styles:
1. Full-Custom Design
- 時間久
- 效能可能較好
- High NRE Cost
2. Standard Cell
3. Gate Array
4. FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device)
- 快
- 效能可能差

#### Comparsion of Design Styles

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### Hardware Description Languages
> HDLs are the major tools for the RTL level and gate level design of VLSI circuits.

#### Major HDLs
1. VHDL (VHSIC HDL)
(VHSIC=Very High Speed Integrated Circuit)
- Sightly better at **system** level
- Language style close to **Ada/Pascal**
- **user-defined** data type, more flexible
2. Verilog
- Slightly better at **gate/transistor** level
- Language style close to **C**
- **Pre-defined** data type, easy to use

### FPGA/CPLD Design Tool - QuartusII

entity OR_gate is
port(
    A, B : in bit;
    C : out bit);
end OR_gate;

architecture OR2_arch of OR_gate is 
begin
    c <= A or B;
end OR2_arch;

*[insulator]: 絕緣體
*[impurities]: 雜質
*[valence]: 電子
*[diode]: 二極體
*[depletion layer]: 空乏區（沒有自由電子跟電洞）
*[positive electrode]: 正極
*[negitive electrode]: 負極
*[MOS]: Metal Oxide Semiconductor 金屬氧化物半導體
*[substrate]: 基座
*[polysilicon]: 聚合矽
*[resin]: 樹脂
*[photoresist]: 光阻劑