---
title: VSLI 0
---
# VLSI Computer-Aided Design for VLSI Design

NTNU VLSI 電腦輔助設計
:arrow_right: [Moodle](https://moodle3.ntnu.edu.tw/course/view.php?id=22039)
##### [Back to Note Overview](https://reurl.cc/XXeYaE)

{%hackmd @sophie8909/pink_theme %}
###### tags: `VLSI` `110-1` `CSIE` `選修` `NTNU`
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## Score
- Homework 40 %
- Homework 1
- Due Day: 11/5
- Homework 2
- Due Day: 12/3
- Midterm 30 %
- Final 30 %

## Outline

- [Ch.01 Introduction to VLSI Design](https://hackmd.io/@NTNUCSIE112/VLSI110-1_1)
- Transistors and Circuit Fabrication
- CMOS Circuits and Logic Gates
- Digital Circuits
- VLSI Design Flow and Style
- Hardware Description Languages
- FPGA/CPLD Design Tool - QuartusII
- [Ch.02 VHDL-Basic Elements and Dataflow](https://hackmd.io/@NTNUCSIE112/VLSI110-1_2)
- Identifiers and Data Objects
- Data Types
- Operators and Attributes
- Dataflow Model
- Entity Declaration and Architecture Body
- Concurrent Signal Assignment
- Conditional Signal Assignment
- Selected Signal Assignment
- [Ch.03 VHDL-Behavior and Structural](https://hackmd.io/@NTNUCSIE112/VLSI110-1_3)
- Process statement
- Variable assignment statement
- Signal assignment statement
- If, Loop, Case, and Wait statements
- Behavior Model and Simulation
- Component declarations
- Component instantiation
- Components provided by Altera
- Hierarchical Design
- Ch.04 VHDL-Advanced
- Ch.05 Registers, Counters and Finite State Machines
- Registers
- Counters
- Finite State Machines
- Ch.06 MIPS Design
- Multicycle 16-bit MIPS with no pipelining
- 8 general purpose registers
- Support R- and I-instruction formats
- Main memory is read-only
- Ch.07 Programmable Logic and Storage Devices
- Programmable Logic Devices (PLD)
- Complex Programmable Logic Devices (CPLD)
- Field Programmable Gate Arrays (FPGA)
- Ch.08 Area, Speed and Power Performance for Programmable Logic Devices
- Speed Performance
- Area Performance
- Speed and Area Optimization
- Power Performance
- Ch.09 Test Bench Design
- Writing a test bench
- CAD tool MODELSIM
- Example: Hardware Design of Random Number Generator
- MODELSIM for QUARTUS II Simulation
- Verilog (Chap. 10, 11)
- VLSI Realization of Digital Filters (Chap. 12, 13)
- Standard Cell Design (Chap. 14)

## Midterm
電腦輔助 VLSI 設計 期中考試資訊
- 考試日期：110 年 11 月 12 日
- 考試時間：下午 2:20 開始，進行 90 分鐘
- 考試地點：
學號最後一碼為雙數者：
理學院 C209 教室（理學院 C 棟二樓）
學號最後一碼為單數或外校者：
理學院大樓 B101 教室（原上課教室）
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## CAD Tools

- Quartus II (Altera)
- Modelsim (Mentor)
- Design Compiler (Synopsis)