[LINUX KERNEL MEMORY BARRIERS](/pxfg3JNFSRqdmObZhApc_g)
===
> [memory-barriers document - The Linux Kernel Archives](https://www.kernel.org/doc/Documentation/memory-barriers.txt)
>> David Howells <[e-mail]>
Paul E. McKenney <[e-mail]>
Will Deacon <[e-mail]>
Peter Zijlstra <[e-mail]>

## DISCLAIMER

This document is not a specification; it is intentionally (for the sake of
brevity) and unintentionally (due to being human) incomplete. This document is
meant as a guide to using the various memory barriers provided by Linux, but
in case of any doubt (and there are many) please ask. Some doubts may be
resolved by referring to the formal memory consistency model and related
documentation at tools/memory-model/. Nevertheless, even this memory
model should be viewed as the collective opinion of its maintainers rather
than as an infallible oracle.

To repeat, this document is not a specification of what Linux expects from
hardware.

The purpose of this document is twofold:

(1) to specify the minimum functionality that one can rely on for any
particular barrier, and

(2) to provide a guide as to how to use the barriers that are available.

Note that an architecture can provide more than the minimum requirement
for any particular barrier, but if the architecture provides less than
that, that architecture is incorrect.

Note also that it is possible that a barrier may be a no-op for an
architecture because the way that arch works renders an explicit barrier
unnecessary in that case.

## CONTENTS

### [Abstract memory access model.](/UE9bkWCyTYGS_AwifL419g)
- Device operations.
- Guarantees.

### [What are memory barriers?](/YHXW_SxfRzCDWsHkQ5TI1A)

- Varieties of memory barrier.
- What may not be assumed about memory barriers?
- Data dependency barriers (historical).
- Control dependencies.
- SMP barrier pairing.
- Examples of memory barrier sequences.
- Read memory barriers vs load speculation.
- Multicopy atomicity.

### [Explicit kernel barriers.](/F1NsdIC9Sh6koXzYYNGY5Q)

- Compiler barrier.
- CPU memory barriers.

### [Implicit kernel memory barriers.](/b2td5B3NTW2ms2JLiSZ7kg)

- Lock acquisition functions.
- Interrupt disabling functions.
- Sleep and wake-up functions.
- Miscellaneous functions.

### [Inter-CPU acquiring barrier effects.](/vcn_3FC9RU-mI-mml-2pVA)

- Acquires vs memory accesses.

### [Where are memory barriers needed?](/MRn5WgIJQR235-ojaLitUg)

- Interprocessor interaction.
- Atomic operations.
- Accessing devices.
- Interrupts.

### [Kernel I/O barrier effects.](/lPyqbhc5RPi1xEp-bfjiQw)

### [Assumed minimum execution ordering model.](/WGySihj4TuimAxvdMS6Hdw)

### [The effects of the cpu cache.](/uKimVoA9TFy2zsMxIE7ZQQ)

- Cache coherency.
- Cache coherency vs DMA.
- Cache coherency vs MMIO.

### [The things CPUs get up to.](/kfHUaA9KTlSh8Kb3hMURmQ)

- And then there's the Alpha.
- Virtual Machine Guests.

### Example uses.

- Circular buffers.
Memory barriers can be used to implement circular buffering
without the need of a lock to serialise the producer with
the consumer. See:

Documentation/core-api/circular-buffers.rst

for details.

### References.

Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
Digital Press)
Chapter 5.2: Physical Address Space Characteristics
Chapter 5.4: Caches and Write Buffers
Chapter 5.5: Data Sharing
Chapter 5.6: Read/Write Ordering

AMD64 Architecture Programmer's Manual Volume 2: System Programming
Chapter 7.1: Memory-Access Ordering
Chapter 7.4: Buffering and Combining Memory Writes

ARM Architecture Reference Manual (ARMv8, for ARMv8-A architecture profile)
Chapter B2: The AArch64 Application Level Memory Model

IA-32 Intel Architecture Software Developer's Manual, Volume 3:
System Programming Guide
Chapter 7.1: Locked Atomic Operations
Chapter 7.2: Memory Ordering
Chapter 7.4: Serializing Instructions

The SPARC Architecture Manual, Version 9
Chapter 8: Memory Models
Appendix D: Formal Specification of the Memory Models
Appendix J: Programming with the Memory Models

Storage in the PowerPC (Stone and Fitzgerald)

UltraSPARC Programmer Reference Manual
Chapter 5: Memory Accesses and Cacheability
Chapter 15: Sparc-V9 Memory Models

UltraSPARC III Cu User's Manual
Chapter 9: Memory Models

UltraSPARC IIIi Processor User's Manual
Chapter 8: Memory Models

UltraSPARC Architecture 2005
Chapter 9: Memory
Appendix D: Formal Specifications of the Memory Models

UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
Chapter 8: Memory Models
Appendix F: Caches and Cache Coherency

Solaris Internals, Core Kernel Architecture, p63-68:
Chapter 3.3: Hardware Considerations for Locks and
Synchronization

Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
for Kernel Programmers:
Chapter 13: Other Memory Models

Intel Itanium Architecture Software Developer's Manual: Volume 1:
Section 2.6: Speculation
Section 4.4: Memory Access