# M4的DAC筆記
###### tags: `M4`

## 參考資料
> - [SAM D5x/E5x Family Data Sheet](https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5x_E5x_Family_Data_Sheet_DS60001507G.pdf)
> Chapter 47. DAC

## 功能方塊圖

## 輸出模式
- Differential Mode
- Single Mode

## 硬體工作時間

- 轉換時間
24倍的colck source週期

## 特殊功能
- Dither
>抖動（英語：Dither），是在數位訊號處理領域的中一項用於降低量化誤差的技術。透過在較低位元中加入雜訊，藉此破壞諧波的排序，使諧波的影響受到壓制，並減少量化誤差在低頻的影響。

來源：[中文Wiki](https://zh.wikipedia.org/wiki/%E6%8A%96%E5%8B%95_(%E6%95%B8%E4%BD%8D%E8%A8%8A%E8%99%9F%E8%99%95%E7%90%86))
- Dithering Mode

>In dithering mode, DATAx is a 16-bit unsigned value where
DATAx[15:4] is the 12-bit data converted by DAC and DATAx[3:0] represent the dither bits.

>The principle is to make 16 sub-conversions of the DATAx[15:4] value or the (DATAx[15:4] + 1) value, so that by
averaging those two values, the conversion result of the 16-bit value (DATAx[15:0]) is accurate.

- Interpolation Mode

## 設定
### I/O PIN
VOUT0 PA2
VOUT1 PA5
AREFA PA3
I/O多工器選擇 B function

### GCLK
Enable 42th Peripheral Channel Control

### DAC
#### 硬體暫存器DACCTRLx
- bits 15:13 (OSR)
> 0 -> no interpolation
1 -> 2x oversampling ratio
2 -> 4x oversampling ratio
3 -> 8x oversampling ratio
4 -> 16x oversampling ratio
5 -> 32x oversampling ratio

- bit 7 (DITHER)
> 1 -> enable
0 -> disable

- bit 6 (RUNSTDBY)
> 0 disabled during standby sleep mode
1 keep working during standby slepp mode

- bits 3:2 (CCTRL)
> 0 if clock source <=1.2MHz
1 if clock source > 1.2MHz && <= 6MHz
2 if clock source > 6MHz && <= 12MHz

- bit 1 (ENABLE)
>DAC周邊內的 DAC0或 DAC1輸出enable

- bit 0 (LEFTADJ)
> 1 -> DATAx & DATABUFx registers are left-adjust(對齊高位)

#### 硬體暫存器CTRLB
- bits 2:1 (REFSEL)
> 0 -> 直接使用外部電源作為reference
1 -> 晶片的VDD ANA作為reference
2 -> 外部電源作為reference, 但有防止外部電源供應電流不足的buffer
3 -> Internal bandgap reference

- bit 0 (DIFF)
>0 -> Single Mode
1 -> Differential Mode

#### 硬體暫存器CTRLA
- bit 1 (ENABLE)
> DAC周邊enable