# [Design Practice Sharing] Developing a Sparse to Continuous Stream Converter IP - - Part II : Functional Specification

## 1. Overview

This IP is designed to convert AXI-Stream sparse format data into a continuous, gap-free AXI-Stream format suitable for high-throughput applications, such as interfacing AXI-MM data with Xilinx CPM QDMA IPs.

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## 2. Design Objectives

### 2.1 Primary Goals

Convert sparse AXI-MM data (with TSTRB marking) into continuous AXI-Stream output.

Handle unaligned start addresses.

Repack data across beats using a cascade mechanism.

Support final beat invalid byte marking.

Maintain data order and integrity.

#### Example:


### 2.2 Additional Design Options

Support for AXIM narrow transfers (i.e., fewer than full bus width bytes per beat), using TSTRB to mark valid bytes.

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## 3. External Interfaces

### 3.1 AXI-Stream Input (Sparse Format)

| Signal | Direction | Width | Description |
| ------------- | --------- | -------- | --------------------------------- |
| `axim_tvalid` | Input | 1 bit | Indicates valid data on input bus |
| `axim_tready` | Output | 1 bit | Ready to accept input data |
| `axim_tlast` | Input | 1 bit | Indicates last transfer in packet |
| `axim_tstrb` | Input | N/8 bits | Byte-wise valid strobe mask |
| `axim_tdata` | Input | N bits | Input data |

> *N: Data bus width (e.g., 32/64/128 bits)*

### 3.2 AXI-Stream Output (Continuous Format)

| Signal | Direction | Width | Description |
| ------------------ | --------- | --------- | -------------------------------------------- |
| `axis_tvalid` | Output | 1 bit | Output data is valid |
| `axis_tready` | Input | 1 bit | Downstream is ready to receive data |
| `axis_tlast` | Output | 1 bit | Marks the last beat of a packet |
| `axis_tfirst` | Output | 1 bit | Marks the first beat of a packet |
| `axis_tstrb` | Output | N/8 bits | Output byte-wise valid indicator |
| `axis_tdata` | Output | N bits | Output data |
| `axis_start_addr` | Output | log2(N/8) | Start address offset of first valid byte |
| `axis_invalid_cnt` | Output | log2(N/8) | Number of invalid bytes in final output beat |

> *N: Data bus width (e.g., 32/64/128 bits)*

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## 4. Functional Behavior

### 4.1 Data Cascade

* If input beat doesn’t fill a full output beat, it is buffered.
* Next input is merged to complete a full AXIS beat.
* Remaining bytes (if any) are stored and cascaded to the next.

### 4.2 Alignment and Shifting

* Based on start address offset, data is shifted to LSB.
* Maintains order of bytes during merging.

### 4.3 Final Beat Handling

* Last beat may contain fewer than full bytes.
* Invalid count is emitted via `axis_invalid_cnt`.

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## 5. Verification Considerations

* Aligned vs unaligned start cases.
* Multi-beat repacking with cascade.
* Partial final beats and invalid count.
* TSTRB correctness under all cases.
* Handshake (TVALID/TREADY) backpressure compliance.

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## 6. Target Application

* Designed to connect AXI-MM sources to streaming interfaces such as **Xilinx CPM QDMA**.
* Suitable for PCIe DMA scenarios requiring high throughput and strict data alignment.

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