---
# System prepended metadata

title: ASOC study

---

## lab1:
這個lab我學到關於fsic 模擬時的testbench 該如何編寫
Soc_UP_mode_write : This task is used to select the user_project for a specified
function
![image](https://hackmd.io/_uploads/rJXbY2LLC.png)
In our case is FIR, so we need to change the value of address 32’h30005000 to 1
![image](https://hackmd.io/_uploads/ryUGKhIUR.png)
2. Explain why “By programming configuration address [‘h3000_5000], signal
user_prj_sel[4:0] will change accordingly”?
Step1. Wishbone protocol is translated into AXI protocol through wb_fsm
Step2. Using the axi_grant_o_reg determines whether the current usage of the
AXI protocol is by the SOC (WB) or the FPGA (like an arbiter : axi_grant_o_reg
-> 0 for wishbone ; axi_grant_o_reg -> 1 for FPGA)
Step3. Axi_fsm determines the current state. If it is idle, the AXI data sent from
the master side (Step2 data) is transferred in
Step4. After receiving the data at the slave end, user_prj_sel is changed
according to the data.
Briefly describe how you do FIR initialization (tap parameter, length) from SOC
side (Test#1).
localparam UP_BASE=32'h3000_0000
Data length (32'h3000_0010) : use WB to write the data length to the specified
address(32'h3000_0010)
Tap parameter (32'h3000_0020 ~ 32'h3000_0048) : use WB to write the tap
parameter to the specified address (32'h3000_0020 ~ 32'h3000_0048)
4. Briefly describe how you do FIR initialization (tap parameter, length) from FPGA
side (Test#2).
localparam FPGA_to_SOC_UP_BASE=28'h000_0000
Data length (28'h000_0010) : use FPGA to write the data length to the specified
address(28'h000_0010)
Tap parameter (28'h000_0020 ~ 28'h000_0048) : use FPGA to write the tap
parameter to the specified address (32'h3000_0020 ~ 32'h3000_0048)
5. Briefly describe how you feed in X data from FPGA side.
Using fpga_as_is_tdata, transmit X data from io_serdes to the user project through
AXI-Stream.
6. Briefly describe how you get output Y data in testbench, and how to do
comparison with golden values
Using fpga_is_as_tdata, transmit Y data from user project to the io_serdes through
AXI-Stream, and build a golden data list to compare with the result captured list

## lab2-1:
這個lab讓我熟悉Catapult的tool操作

## lab2-2:
這個lab則是修改HLS code 來符合edgedetect的功能
How you design your work ( 5 modifications)
(一) Process four pixels per clock cycle
將 input data 改成 1 個 clk 進來 4 個 Byte 的 pixel 因此需要先將 input data
type 改成 1 word ，如下圖
![image](https://hackmd.io/_uploads/rJSWo3LUC.png)
進入 Vertical block
![image](https://hackmd.io/_uploads/SkSmj2U8A.png)
每一次會讀 4 個 pixel，讀兩筆資料後，一起存進 64 bit 的 line buffer 中，等到
那一列的 line buffer 存滿，便可與下一列的讀進來的資料進行運算，因此為
vertical 運算
進入 horizontal block
![image](https://hackmd.io/_uploads/HJCVon8IC.png)
每一次會讀 4 個 pixel，但一次只使用前一次舊的兩個 pixel 和新的 1 個 pixel，
做一次 grad 的運算後，再將 4 個 pixel 中的新的第 2 個 pixel、新的第 1 個
pixel、急舊的最後一個 pixel 做運算，以此類推。
(二) Use sum of absolute difference (SAD) for edge magnitude calculation
將 vertical block 計算出的 dy 取絕對值與 horizontal block 算出的 dx 取絕對
值相
![image](https://hackmd.io/_uploads/r138s28IC.png)
(三) Add two crc32 calculation on image input / output.
將輸入與輸出都做 crc32 calculation
![image](https://hackmd.io/_uploads/Byxusn8IR.png)
(四) Select the output source from input image or the calculated magnitude.
如果 sw_in 為 0 輸出為 pix_in，否則為經過 SAD 運算的 magn
![image](https://hackmd.io/_uploads/ry6Fs2LUC.png)
(五) Remove the angle calculation.
將原本 angle 計算刪除

## lab3:
這個lab主要是學習snps-flow的每個步驟再幹嘛
![image](https://hackmd.io/_uploads/BJk4nhIUC.png)

![image](https://hackmd.io/_uploads/B1NS32UIA.png)
![image](https://hackmd.io/_uploads/B18U33I8C.png)
![image](https://hackmd.io/_uploads/H1uw23LLA.png)
![image](https://hackmd.io/_uploads/SkVO33ULR.png)
![image](https://hackmd.io/_uploads/S11F3388C.png)
![image](https://hackmd.io/_uploads/Byxjh3LIA.png)
![image](https://hackmd.io/_uploads/S1th2nUL0.png)
![image](https://hackmd.io/_uploads/rJPp3hUI0.png)
![image](https://hackmd.io/_uploads/Skt0228LA.png)
![image](https://hackmd.io/_uploads/SyQ16h88R.png)
## lab4:
這個lab主要是學習如何驗證fsic-fpga 的功能是否正確

Discussion and observation
1. 雖然沒有修改 hls_userdma，但有稍微研究一下程式碼。由於 BUF_LEN 是
一固定數值，因此這個 DMA 只能用來傳固定大小的資料，這也明顯不是一
個好的設計。
2. 一開始在產生 fir 的 input 資料時並沒有限制數值的大小範圍，後來發現一些
過大的數會導致計算 fir 時發生 overflow，而軟體在處理 overflow 時與 fir 不
完全相同，進而導致軟體計算的結果與硬體不同。於是我在產生 input data
時將所有 input data 限制在-200 到 200 之間，來避免 overflow 發生。
Debugging experience
1. Program 完 fir 後想把值讀出來檢查時失敗
於是我看著波形圖，一層一層檢查最後才發現是 User_subsys/axil_slav.v 裡
面有問題
2. Fir 收到重複資料
順著資料傳送的路徑檢查，發現是 As 到 is 有問題
3. Pynq 卡死
執行 python code 前要確認讀寫的位置是否正確，不然如果讀寫的位置沒有
東西可以回應，pynq 會一直等待，導致系統卡死。另外 onlineFPGA 似乎也
有一些問題，有些板子即使顯示 available 並且能成功租借，但是卻無法連
上板子
## final project:
Purpose
AES-128(Advanced Encryption Standard) is a symmetric encryption
algorithm that encrypts and decrypts data using a fixed-length key (128 bits).
AES-128 can be used to protect the privacy of sensitive data, ensuring security
during transmission and storage.
⚫ Project scope
(一) system block design
![image](https://hackmd.io/_uploads/ByiLA3LLR.png)
![image](https://hackmd.io/_uploads/HJqwA28IA.png)
(二) Encryption process
![image](https://hackmd.io/_uploads/Hkq_Ah8L0.png)
Implementation Process
1. Study AES standard and implement the algorithm in C++
2. Test the implementation with test vectors released by NIST
3. Write HLS code and generate rtl using Catapult
4. Modify original design and complete hls code
5. Integrate it into fsic and modify testbench to complete AES 128 simulation and
verification

