---
# System prepended metadata

title: Block Design & IP Catalog
tags: [vivado練習]

---

# Block Design & IP Catalog

- [IP & Block Design](https://medium.com/@sienna.a0522d/ip-block-design-dc8d34d58677) ←之前寫的，但我覺得有些地方不太清楚，所以這篇就誕生了。
- 這篇主要是教把自己寫的Verilog (.v檔) & IP Catalog 拉到Block Design連接

## Step 1 建立.v檔
add design sources.
![](https://hackmd.io/_uploads/H10PzEzU2.png)


我的code，dina&addra跟著cnt變化，藉此給後面連接的ram data.
```
module test1(
    input               clk,  
    input               rst_n, 
    output              ram_en, 
    output              ram_wea,  
    output  reg [7:0]  ram_addr,  
    output  reg [7:0]  ram_dina, 
    //input       [7:0]  ram_rd_douta   
    );
    
reg [5:0]  rw_cnt ;  
 
 assign ram_en = 1;
 assign ram_wea = (rw_cnt <= 6'd31) ? 1'b1 : 1'b0;
 
 always @ (posedge clk)begin
        if (rw_cnt == 6'b111111) begin
            rw_cnt <= 6'b000000;   // 將計數器重置為初始值
        end 
        else begin
            rw_cnt <= rw_cnt + 1;   // 計數值增加
        end
 end
 
  always @ (posedge clk)begin
        if ( rw_cnt < 6'd31)begin
        ram_dina <= 1 ; 
        end
        else begin
        ram_dina <= 0 ; 
        end
  end    
endmodule
```

## Step 2 建立IP Catalog

左鍵點擊，選擇block memory那個，之後跳到Cutomize IP
![](https://hackmd.io/_uploads/HkiT2VQIh.png)
![](https://hackmd.io/_uploads/SyJIcHXU3.png)





|    按OK後出現這個，選Global，再按Generate (如果選錯也沒事，後面可以補救)     |           會生成這個，前面會白白的            |
|:---------------------------------------------:|:---------------------------------------------:|
| ![](https://hackmd.io/_uploads/HJ-lIOm83.png) | ![](https://hackmd.io/_uploads/SkeOnwQLh.png) |


選IP Sources，點.veo檔，把籃框位置copy
![](https://hackmd.io/_uploads/HyeanDX8n.png)

創一個 design sources. 把剛剛的東西貼上來，再加些細節(input / output那些)
![](https://hackmd.io/_uploads/S1nbSYmU3.png)


```
module ram(
    input   clka,
    
    output   ena,
    output   wea,
    output   addra,
    output   dina,
    output  douta
    );
    
blk_mem_gen_1 your_instance_name (
  .clka(clka),    // input wire clka
  .ena(ena),      // input wire ena
  .wea(wea),      // input wire [0 : 0] wea
  .addra(addra),  // input wire [3 : 0] addra
  .dina(dina),    // input wire [15 : 0] dina
  .douta(douta)  // output wire [15 : 0] douta
);
endmodule
```

mem.就會出現在下面，且前面是白白的
![](https://hackmd.io/_uploads/SkK4cu7Ih.png)


## Step 3 拉到Block Design

把前面坐的直接按住拖過去
![](https://hackmd.io/_uploads/ByLY0_mIn.png)

Do Re Mi So~
![](https://hackmd.io/_uploads/ryrQHK7Ih.png)

把它連接起來
![](https://hackmd.io/_uploads/Byb-MYEI3.png)

### error Debug
如果前面如果前面這邊沒選到Global，會拉不進block裡，出現error
![](https://hackmd.io/_uploads/SkHnPYVL3.png)

- [filemgmt 56-328] Reference 'test2' contains sub-design file 'c: file location', which is configured for out-of-context synthesis. OOC sub-designs are not allowed in the reference. To change the setting, use TCL command: 'set_property generate_synth_checkpoint 0 [get_files blk_mem_gen_1.xci]'.
- [BD 41-1690] Unable to resolve module-source based on inputs: test2
- [BD 5-7] Error: running create_bd_cell  -type module -reference test2 -name test2_0 .

*第一個error後面use TCL command: 'setproperty generatesynthcheckpoint 0 [getfiles blkmemgen1.xci]'. 可以複製''內的東東到Tcl Console內，error會消失*

可以照下面步驟
| 1. | 2. |
| -------- | -------- |
| ![](https://hackmd.io/_uploads/r129kKm83.png) | ![](https://hackmd.io/_uploads/BJ8nyFXUh.png) |


## Step 4 Creater HDL Wrapper


|  1.右鍵design_1，按Genrate | 2.按Genrate  |
| -------- | -------- |
| ![](https://hackmd.io/_uploads/rysG-KQL2.png)  | ![](https://hackmd.io/_uploads/Hk0J7K7L3.png) |
| 3.右鍵design_1，按Creater HDL Wrapper | 4. 按ok |
| ![](https://hackmd.io/_uploads/BJ1WVK7L3.png)| ![](https://hackmd.io/_uploads/ryJe4tQUn.png) |

***有改動到block design裡的設計都重新執行1.2.，重新生成***

完成後長這樣，之後模擬步驟都跟之前一樣
![](https://hackmd.io/_uploads/ByXEVYELn.png)

大致就是這樣，如果遇到問題會再補充





