SOC LAB Study Record
===

SOC Lab
---
- [Gotchas_101 : Stuart Ch4 & Ch5](https://hackmd.io/@soclabteam/B18l4LV5h)
- [AXI4-Stream](/yKa8kAHyT9CZtNdywFcNFA)
- [AXI4-Lite](/Mz8U18ItT1e2tV8UU5esiw)
- [Lab 3 Report](/K5sbkfPRTg-fzd2DsXv8tw)
- [Lab 6 Report](/og0rSR2NTR2f5rnDs1wa2A)
- [SOC Lab Final Project](https://hackmd.io/_-2HoA1rRuiNKHXRXIWBLA)

Verilog
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### NTU CVSD Study journal
- [Part 1 & 2](/NSJiEI37QamcdMDf-0uibw)
- [Part 3](/QJC80QjkRcWyVjdkE5nmdQ)
- [Part 4](/DtspUfczQ36n1tb1j0oqmQ)

Vitis-HLS
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- [Combinational Circuit](/8HlmuEhxRlOlFHJ72NwkwA)
- [Sequential Circuit](/gtP8wJAzSEO485OhQ6uCSQ)

Catapult-HLS
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- [EdgeDetect](/t6FczfuAQH6YPZWHBQDUJg)

Post Quantum Cryptography
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- [Post Quantum Cryptography Preview](/CbR98ty4Qf6lIVRe2TJZVw)
- [Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators](/iuMB_NiKTB-Mu9EGZtnzmA)
- [High-Level Synthesis for Hardware Implementation of Cryptography: Experience Feedback](/Q9TWwFx1SvaLZSJ3ExZfxQ)
- [High-Level Synthesis design approach for Number-Theoretic Multiplie](/JrWs1zM6RTWDbHSdbkQdhQ)
- [Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis](/AL-3LnHcTrqSPlNK7Hi3LQ)
- [A Flexible and Scalable NTT Hardware](/0i_Hs02eRP6t2IZ3DJxczA)
- [Function Study](/3BMkwvcPRD-Xy6dL3juv7A)