---
# System prepended metadata

title: EESM6000C Week 6 Homework

---

Student ID: 20726557

# Caravel_hk_gpio_spi_mmio
### Explain the Caravel RISC-V firmware code update, and boot-up sequence, it involves
#### 1. Using passthru-mode to update spiflash
####  2. CPU code fetch from spi-flash

![image](https://hackmd.io/_uploads/HkO8mKDAJg.png)

The Caravel RISC-V firmware code update and boot-up sequence involves using passthru-mode to update SPIFlash and fetching the CPU code from the SPIFlash.

To update the SPIFlash, passthru-mode is used. Pass-thru mode puts the CPU into reset to halt the CPU operation and become inactive. It will then set FLASH_CSB to low to initate data transfer with the SPIFlash. The SPI signals SDI, SCK, FLASH_IO1 is routed to FLASH_IO0, FLASH_CLK, SDO respectively and data is transfered to the SPIFlash. The firmware code is transfered and written to the SPIFlash. After updating the data on the SPIFlash, passthru-mode is disabled, which raises the FLASH_CSB to terminate the data transfer. CPU is brought out of reset and starts executing instructions at the program start address.

The boot-up sequence involves fetching the CPU code from the SPI Flash. The CPU is first brought out of reset phase to initialize all registers. The CPU is designed to start exectuing instructions from the program start address. In the case of the Caravel RISC-V, the CPU will fetch the instruction from the SPIFlash through the SPI interface. The SPIFlash will begin data transfer through the SPI interface to the CPU. The CPU will execute the firmware code from the SPIFlash once it is transferred.


### GPIO(MPRJ) can be used for management core or user-project, explain how to program mprj 
#### 1. What is the MMIO address to configure each MPRJ pin
#### 2. Which bit is used to set the MPRJ used by the management core or the user
#### 3. illustrate by code  (reference the firmware code)

1. The MMIO registers is part of the housekeeping of the Caravel Harness Chip. There are specific addresses to configure each MPRJ pin. The housekeeping region address is 0x26000000, and the offset to configure the MPJR pins are 0x24-0xB8. Therefore, to access mprj_io[37], the address will be 0x260000B8.

2. Bit[0] of the mprj_io control registers is used to control the Management Control Enable. When Bit[0] is 0, it is user control. When Bit[0] is 1, it is management control. By default, the value is set to 1.

3. 
```
module mprj_io #(
    parameter AREA1PADS = `MPRJ_IO_PADS_1,
    parameter TOTAL_PADS = `MPRJ_IO_PADS
) (
    inout vddio,
    inout vssio,
    inout vdda,
    inout vssa,
    inout vccd,
    inout vssd,

    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,

    input vddio_q,
    input vssio_q,
    input analog_a,
    input analog_b,
    input porb_h,
    input [TOTAL_PADS-1:0] vccd_conb,
    inout [TOTAL_PADS-1:0] io,
    input [TOTAL_PADS-1:0] io_out,
    input [TOTAL_PADS-1:0] oeb,
    input [TOTAL_PADS-1:0] enh,
    input [TOTAL_PADS-1:0] inp_dis,
    input [TOTAL_PADS-1:0] ib_mode_sel,
    input [TOTAL_PADS-1:0] vtrip_sel,
    input [TOTAL_PADS-1:0] slow_sel,
    input [TOTAL_PADS-1:0] holdover,
    input [TOTAL_PADS-1:0] analog_en,
    input [TOTAL_PADS-1:0] analog_sel,
    input [TOTAL_PADS-1:0] analog_pol,
    input [TOTAL_PADS*3-1:0] dm,
    output [TOTAL_PADS-1:0] io_in,
    output [TOTAL_PADS-1:0] io_in_3v3,
    inout [TOTAL_PADS-10:0] analog_io,
    inout [TOTAL_PADS-10:0] analog_noesd_io
);

    wire [TOTAL_PADS-1:0] loop0_io; // Internal loopback to 3.3V domain ground
    wire [TOTAL_PADS-1:0] loop1_io; // Internal loopback to 3.3V domain power
    wire [6:0] no_connect_1a, no_connect_1b;
    wire [1:0] no_connect_2a, no_connect_2b;
boledu_io io_pad[TOTAL_PADS -1: 0] (
 .io(io[TOTAL_PADS-1:0]),
 .io_out (io_out[TOTAL_PADS - 1:0]),
 .oeb( oeb[TOTAL_PADS-1:0]),
 .io_in ( io_in[TOTAL_PADS-1:0])
);


endmodule


module boledu_io( inout io,
       input io_out,
       input oeb,
   output io_in);
 // bufif0(io_in, io, oeb);
 assign io_in = io;
 bufif0(io, io_out, oeb);
 pullup (io);

endmodule
```

---

# caravel_intr_sram_wb_usrprj_firmware
### Explain the procedure/code to move code from spiflash to dff 
![image](https://hackmd.io/_uploads/SJyEHswAJx.png)

The procedure to move the code from SPIFlash to DFF is through the Wishbone Interface. THere is a Master and Slave Wishbone components on the BUS. DFF is one of the Wishbone Slave memory region. When the Wishbone receives an input to write into DFF, the Wishbone interface will choose the DFF as the slave selection and output the data to the DFF.

### List the user project interface signals (ref: the user_project wrapper.v) 
#### What memory address is used to access the user project?
![image](https://hackmd.io/_uploads/r1W0vsw0Jl.png)

The following is the user interface signals for the project
```
module user_project_wrapper (
    // Wishbone Slave ports (WB MI A)
    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

    // Logic Analyzer Signals
    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,

    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

    // Analog (direct connection to GPIO pad---use with caution)
    // Note that analog I/O is not available on the 7 lowest-numbered
    // GPIO pads, and so the analog_io indexing is offset from the
    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
    inout [`MPRJ_IO_PADS-10:0] analog_io,

    // Independent clock (on independent integer divider)
    input   user_clock2,

    // User maskable interrupt signals
    output [2:0] user_irq
);
```

The memory address used to access the user project is 0x30000000-0x3FFFFFFF

### Explain the counter_WB example, Verilog testbench, and firmware C code
![image](https://hackmd.io/_uploads/Sk455jv0yx.png)
The counter_WB example demonstrates the configuration of the MPRJ_IO and checking.

The Verilog testbench checks the values of the mprj_io[31:16] with its coresponding flag values.
![image](https://hackmd.io/_uploads/BkPGqjvA1g.png)

The firmware C code enables wb of the MPRJ_IO and configures the MPRJ_IO as the output, assigning the flag.
![image](https://hackmd.io/_uploads/B1lEcjwRyl.png)

---
	
# caravel soc - lab4-0
### Observe Caravel SoC simulation, show waveforms with related signals

Please refer to the Hack-MD of Lab 4-0.
https://hackmd.io/@JokerAnthonio/rJuTktL01g