Student ID: 20726557

# Cache
### Calculate cache size and tag addresses

The total cache size is the following:
> 64 Byte/Cacheline * 4096 Cachelines = 262144 Byte = 256 KB
> 256 KB * 4 way = 1024 KB total cache size

The address range of the tag is the following (assuming byte addressable):
> Offset = log2(64) = 6 Bits
> Index = log2(4096/4) = 10 Bits
> Address Range = 16 Bits

### MESI protocol exercise

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# Memory
### Memory system performance improvement techniques

### Access array elements in storage order

Code A gives better performance. Since the array is in row-major order, by accessing the data at across each row allows better spatial locality and improves the performance.

### DRAM address mapping

How many memory channels?
> 1 Channel Bit --> 2 Channels

How many DIMMs are in each channel?
> 1 DIMM Bit --> 2 DIMMs per Channel

How many banks are in each DIMM?
> 2 Bank Bits --> 4 Bank per DIMM

Which CPU address bit for dataset size of 265B?
> 265B --> 512B, log2(512) = 9 --> Bit[8]