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# System prepended metadata

title: Module and Dp State Logics

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# Module and Dp State Logics

## 1. Module State Machine

![image](https://hackmd.io/_uploads/r1Hc_Va9lg.png)


<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 1 Module State Machine</div>

The diagram above shows the end‐to‐end flow of the Module State Machine, with arrows indicating which transition signals drive each move between states. In particular, any time ResetS is asserted (from any state except Reset) the machine immediately enters the Resetting state, and once the reset sequence completes it returns to Reset. From there, ResetS deasserting kicks off MgmtInit, then on to ModuleLowPwr, ModulePwrUp, and finally ModuleReady (or into ModuleFault if FaultS ever asserts).

Below is the table that defines the priority of exit conditions: if more than one transition signal is true at the same instant, the machine always honors ResetS first, FaultS second, and all other signals (LowPwrS, LowPwrExS, "complete" flags) last.

### Steady vs. Transient States

In the diagram, any state drawn with sharp corners is a steady state—the module remains there indefinitely until one of its exit signals becomes true. By contrast, states drawn with rounded corners are transient—the module automatically proceeds to the next state as soon as its internal "complete" or shutdown sequence finishes.

- **Reset, ModuleLowPwr, ModuleReady, and ModuleFault** are steady states.
- **Resetting, MgmtInit, ModulePwrUp, and ModulePwrDn** are transient states.

Transient states rely on their own autonomous behavior (e.g. power-down, register initialization, power-up, power-down) to generate a "complete" condition that drives the next transition, whereas steady states wait for external transition signals (ResetS, FaultS, LowPwrS, LowPwrExS) to force an exit.

| Priority | Exit Condition |
|----------|----------------|
| 1 | ResetS |
| 2 | FaultS |
| 3 | All other exit conditions |

**Table 1 Module State Machine exit condition priority**

### Truth Tables and Logics Equations

On module power-up, the MSM always starts in Reset. It stays in Reset while ResetS is asserted; see Table 2 below for how VccReset, the hardware Reset line, and SoftwareReset combine to generate ResetS.

Once ResetS is false, the machine advances into ModuleLowPwr. In that state, the LowPwrS signal (driven by LowPwrRequestSW, LowPwrAllowRequestHW and LowPwrRequestHW) governs whether the module stays in low-power or powers up.

After power-up completes, the module enters ModuleReady. To go back to low-power, LowPwrExS must assert—which requires LowPwrS = 1 and all datapath lanes deactivated.

<div style="display: flex; justify-content: center; gap: 24px; margin: 16px 0;">

<!-- Table 2 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">VccReset (low Vcc)</th>
<th style="border: 1px solid #333; padding: 6px 12px;">Reset (hw)</th>
<th style="border: 1px solid #333; padding: 6px 12px;">SoftwareReset</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>ResetS</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">ASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">ASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">Table 2 ResetS transition signal truth table</figcaption>
</figure>

<!-- Table 3 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">LowPwrRequestSW</th>
<th style="border: 1px solid #333; padding: 6px 12px;">LowPwrAllowRequestHW</th>
<th style="border: 1px solid #333; padding: 6px 12px;">LowPwrRequestHW</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>LowPwrS</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">ASSERTED</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">DEASSERTED</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">Table 3 LowPwrS transition signal truth table</figcaption>
</figure>

<!-- Table 4 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">LowPwrS</th>
<th style="border: 1px solid #333; padding: 6px 12px;">ModuleDeactivatedT</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>LowPwrExS</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">Table 4 LowPwrExS transition signal truth table</figcaption>
</figure>

</div>

### State Transition signals and their Truth table logics along with the dependencies

| Signal | Definition | Logic Equation |
|--------|------------|----------------|
| ResetS | "Generic reset" transition, drives entry into Resetting from any state. | ResetS = VccReset OR Reset OR SoftwareReset |
| FaultS | Module's internal fault summary—assert to enter ModuleFault from any state except Reset/Resetting. | implementation-specific |
| LowPwrS | "Request low-power" – when TRUE, module moves (or stays) in Low-Power mode (ModuleLowPwr or ModulePwrDn). SW and HW can both drive it, with HW gated by an "allow" bit. | LowPwrS = ASSERTED(LowPwrRequestSW OR (LowPwrAllowRequestHW AND LowPwrRequestHW)) |
| LowPwrExS | "Exit low-power" – when TRUE in ModuleReady, triggers power-down (ModulePwrDn). | LowPwrExS = LowPwrS AND ModuleDeactivatedT |

**Table 5**

#### ResetS
- **Logic equation**: ResetS = ASSERTED(VccReset) OR ASSERTED(Reset) OR SoftwareReset
- **Truth table**: See Table 2
- **Components**:
  - **VccReset** (See Table 6): optional generic hardware signal, asserted when one or more V<sub>cc</sub> rails drop below an implementation-defined threshold.
  - **Reset (hw)** (See Table 6): host's hardware reset line. Must be asserted longer than the minimum reset‐pulse width (see form-factor docs & Appendix A).
  - **SoftwareReset** (See Table 6): self-clearing bit that, when written 1, mimics the hardware Reset for the required hold time.

#### LowPwrS
- **Logic equation**: LowPwrS = LowPwrRequestSW OR (LowPwrAllowRequestHW AND ASSERTED(LowPwrRequestHW))
- **Truth table**: See Table 3
- **Components**:
  - **LowPwrRequestSW** (See Table 6): software request to enter or remain in Low-Power mode.
  - **LowPwrAllowRequestHW** (See Table 6): enables evaluation of the external LowPwrRequestHW signal.
  - **LowPwrRequestHW** (See Table 6): external hardware "halt/start-up" low-power request line.
- **Default power-up values**:
  - LowPwrRequestSW = 0
  - LowPwrAllowRequestHW = 1

Module powers up under hardware control (LowPwrRequestHW). To pause startup in ModuleLowPwr, assert LowPwrRequestHW before or during initialization.

#### LowPwrExS
- **Logic equation**: LowPwrExS = LowPwrS AND ModuleDeactivatedT
- **Truth table**: See Table 4
- **ModuleDeactivatedT** (See Table 6): TRUE only when every datapath lane's DPStateHostLaneᵢ = DPDeactivated.
- **Role**: signals exit from ModuleReady back to ModulePwrDn (and eventually ModuleLowPwr) once the module has been quiesced.

#### FaultS
- **Definition**: module-specific fault summary signal
- **Truth table & logic**: implementation-dependent (not defined by CMIS).

| Transition Signal | Reg. Field Name | Location | Description | Spec Table |
|-------------------|-----------------|----------|-------------|------------|
| SoftwareReset | SoftwareReset | Lower Memory, Byte 26 bit 3 | Self-clearing write-only bit; asserting = module reset (holds reset until bit auto-clears) | 8-11 |
| LowPwrRequestSW | LowPwrRequestSW | Lower Memory, Byte 26 bit 4 | SW request for module to enter or remain in Low-Power mode | 6-12 (and 8-11) |
| LowPwrAllowRequestHW | LowPwrAllowRequestHW | Lower Memory, Byte 26 bit 6 | Enables internal evaluation of the external LowPwrRequestHW signal | 6-12 (and 8-11) |
| LowPwrRequestHW | (external) | ----------- | External HW "halt/start-up" low-power request | 6-12 (and 8-11) |
| ModuleDeactivatedT | DPStateHostLane | Page 11h, Byte128 - 131 | "Deactivated" flags for each datapath lane (used by LowPwrExS logic – Table 4) | 6-13 |
| Reset (hw) | (external) | external pin | Host's hardware reset line | 6-11 |
| VccReset | (hardwired) | external power | Generic low-Vcc reset | 6-11 |
| FaultS | (impl.-specific) | internal logic | Module's fault summary signal; asserted on any safety/critical fault | 6-10 |

**Table 6**

### ModuleStateChangedFlag

- A dedicated flag that signals "entry into a new state."
- Asserted only on transitions into ModuleFault, ModuleLowPwr, and ModuleReady as defined in Table 7.
- Suppressed if the module immediately exits that state because its exit condition was already satisfied on entry—preventing notifications for transient, intermediate states.

| New State | ModuleStateChangedFlag |
|-----------|------------------------|
| Resetting | No |
| Reset | No |
| MgmtInit | No |
| ModuleFault | Yes |
| ModuleLowPwr | Yes |
| ModulePwrUp | No |
| ModuleReady | Yes |
| ModulePwrDn | No |

**Table 7**

### Lower Memory byte 8 bit 0

The global status word lives in byte 3 of the module's lower‐memory space. Within that byte, the bits 7–4 is reserved, bits 3–1 encode the current ModuleState, and bit 0 flags the interrupt output (1 = not asserted by default, 0 = asserted). ModuleState is a 3-bit code:

- **001** = ModuleLowPwr
- **010** = ModulePwrUp
- **011** = ModuleReady (flat memory modules report only this state)
- **100** = ModulePwrDn
- **101** = ModuleFault

Codes 000, 110 and 111 are reserved.

### Module State Behaviors

![image](https://hackmd.io/_uploads/SJlJYE6cgx.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 2 Resetting State (Shutting Down)</div>

![image](https://hackmd.io/_uploads/BkuytV6cxg.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 3 Reset State (Ground State)</div>

![image](https://hackmd.io/_uploads/S1zgYN6ceg.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 4 MgmtInit State (Initializing Management Interface)</div>

![image](https://hackmd.io/_uploads/HkcgFE6qxe.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 5 ModuleLowPwr State (Basic Manageability)</div>

![image](https://hackmd.io/_uploads/B1k-FNaqxl.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 6 ModulePwrUp state (Powering Up)</div>

![image](https://hackmd.io/_uploads/ByO-YNacgx.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 7 ModuleReady State (Fully Operational)</div>

![image](https://hackmd.io/_uploads/rkfzt4Tcgx.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 8 ModulePwrDn State (Powering Down)</div>

## 2. Data Path State Machine

![Uploading file..._yc1975c3q]()

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 9 Data Path State Machine</div>

### Truth Tables and Logics Equations

<div style="display: flex; justify-content: center; gap: 24px; margin: 16px 0;">

<!-- Table 8 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;" border="1">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">ModuleReadyT<br>(MSM term)</th>
<th style="border: 1px solid #333; padding: 6px 12px;">LowPwrS<br>(MSM, Table 4)</th>
<th style="border: 1px solid #333; padding: 6px 12px;">DPDeinitT<br>(term)</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>DPDeinitS<br>(transition signal)</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">
Table 8 DPDeinitS transition signal truth table
</figcaption>
</figure>

<!-- Table 9 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;" border="1">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">DPDeinitS<br>(transition signal)</th>
<th style="border: 1px solid #333; padding: 6px 12px;">DPReinitT<br>(term)</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>DPReDeinitS<br>(transition signal)</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">
Table 9 DPReDeinitS transition signal truth table (default)
</figcaption>
</figure>

<!-- Table 10 -->
<figure style="margin: 0; text-align: center;">
<table style="border-collapse: collapse; text-align: center;" border="1">
<thead>
<tr>
<th style="border: 1px solid #333; padding: 6px 12px;">DPReDeinitS</th>
<th style="border: 1px solid #333; padding: 6px 12px;">DPTxDisableT</th>
<th style="border: 1px solid #333; padding: 6px 12px;">DPTxForceSquelchT</th>
<th style="border: 2px solid #333; padding: 6px 12px;"><strong>DPDeactivateS</strong></th>
</tr>
</thead>
<tbody>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 1px solid #333; padding: 6px 12px;">0</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>0</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
<tr>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">X</td>
<td style="border: 1px solid #333; padding: 6px 12px;">1</td>
<td style="border: 2px solid #333; padding: 6px 12px;"><strong>1</strong></td>
</tr>
</tbody>
</table>
<figcaption style="font-size: 0.9em; margin-top: 4px; font-weight: bold;">
Table 10 DPDeactivateS transition signal truth table
</figcaption>
</figure>

</div>

### Truth Tables + Mathematical equations to capture logic

| Signal | Components | Logic Equation |
|--------|------------|----------------|
| DPDeinitS | ModuleReadyT(MSM), LowPwrS(See Table 4), DPDeinitT | DPDeinitS = (NOT ModuleReadyT) OR LowPwrS OR DPDeinitT |
| DPReDeinitS - Case 1 | DPDeinitS(See Table 9), DPReinitT | DPReDeinitS = DPDeinitS OR DPReinitT |
| DPReDeinitS - Case 2 | DPDeinitS | DPReDeinitS = DPDeinitS |
| DPDeactivateS | DPReDeinitS(See Table 10), DPTxDisableT, DPTxForceSquelchT | DPDeactivateS = DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT |

**Table 11**

#### Case 1: Intervention-Free Reconfiguration Supported
When the module supports intervention-free reconfiguration (SteppedConfigOnly = 0), the DPReinitT term is included to detect pending lanes, so DPReDeinitS = DPDeinitS OR DPReinitT.

#### Case 2: Intervention-Free Reconfiguration Not Supported
When the module does **not** support intervention-free reconfiguration, the DPReinitT term is omitted and DPReDeinitS simplifies to DPDeinitS, so ApplyDPInit has no effect on the DPSM.

| Signal | Location | Logic Equation |
|--------|----------|----------------|
| DPDeinitT | Page 10h byte 128 | DPDeinitLane<N> OR DPDeinitLane<N+1> … OR DPDeinitLane<N+M-1> |
| DPTxDisableT | Page 10h byte 130 | OutputDisableTx<N> OR OutputDisableTx<N+1> … OR OutputDisableTx<N+M-1> |
| DPTxForceSquelchT | Page 10h byte 132 | OutputSquelchForceTx<N> OR OutputSquelchForceTx<N+1> … OR OutputSquelchForceTx<N+M-1> |
| DPReinit | Page 11h byte 235 | DPInitPendingLane<N> OR DPInitPendingLane<N+1> ...OR DPInitPendingLane<N+M-1> (See Table 15) |

**Table 12**

### Data Path State Behaviors

![image](https://hackmd.io/_uploads/SkJBK4Tqgx.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 10 DPDeactivated State (Ground State)</div>

![image](https://hackmd.io/_uploads/HyBSYNpcxe.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 11 DPInit State (Initializing)</div>

![image](https://hackmd.io/_uploads/Sk6HYNTqeg.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 12 DPInitialized State (Initialized)</div>

![image](https://hackmd.io/_uploads/rkQLtVaqex.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 13 DPDeinit State (Deinitializing)</div>

:::warning
Note: If LowPwrS become TRUE, this will deactivate all Data Paths in the module (See Figure 5)
:::

![image](https://hackmd.io/_uploads/rkjIYVpcgg.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 14 DPTxTurnOn State (Turning On)</div>

![image](https://hackmd.io/_uploads/SyGvK4aqel.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 15 DPActivated State (Operational)</div>

![image](https://hackmd.io/_uploads/By3wYEa9ee.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 16 DPTxTurnOff State (Turning Off)</div>

### Data Path State Changed Flag

| DPSM State | Output Status Tx | DPStateChangedFlag May Be Set |
|------------|------------------|-------------------------------|
| DPDeactivated | Quiescent | Yes |
| DPInit | Quiescent | No |
| DPInitialized | Depends on per-lane OutputDisableTx and OutputSquelchForceTx settings | Yes |
| DPDeinit | In transition | No |
| DPTxTurnOn | In transition | No |
| DPTxTurnOff | In transition | No |
| DPActivated | Operational | Yes |

**Table 13 Tx Output and DPStateChangedFlag**

- **"Quiescent"** means the Tx outputs are inactive (disabled/squelched).
- **"Operational"** means Tx outputs are actively transmitting.
- **"In transition"** means Tx outputs are changing state (intermediate transient states).
- **DPStateChangedFlag** indicates whether the flag is set when entering the specified DPSM state.

### Control Set

| Bits | Field | Description / Usage | Type |
|------|-------|---------------------|------|
| 7-4 | AppSelCode | Assigns an Application to a lane.<br>- Identifies the Application Descriptor number.<br>- Value 0000b = lane unused (DPDeactivated state).<br>- Multi-lane Data Paths must share the same AppSelCode value. | RW (required) |
| 3-1 | DataPathID | Identifies the Data Path by the lowest lane number of all lanes within the path.<br>- Ignored if lane is unused.<br>- Multi-lane Data Paths must have identical DataPathID. | RW (required) |
| 0 | ExplicitControl | Determines source of Signal Integrity (SI) settings:<br>- 0b = Application-dependent settings (module default).<br>- 1b = Use host-defined SI settings explicitly from the Staged Control Set.<br>- Ignored if lane unused. | RW (required) |

**Table 14 Control Set Content**

#### Key Notes:
- Each lane within a multi-lane Data Path must share identical AppSelCode and DataPathID values.
- ExplicitControl determines if the lane uses default (module-derived) SI settings or host-defined settings.
- Unused lanes have AppSelCode set to 0000b, placing the lane in a DPDeactivated state.

#### Register Specification Reference:
- Defined in CMIS Spec: Table 8-71 (DPConfigLane<i>) (Page 197, OIF-CMIS-05.3)
- Active Control Set Table 8-93 Page 11h, Byte 206-213
- Stage Control Set 0 Table 8-72 Page 10h, Byte 145-152
- Stage Control Set 1 Table 8-77 Page 10h, Byte 180-187

### Applying a Staged Control Set

![image](https://hackmd.io/_uploads/S1rutEaqlx.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 17 Control Set Configuration Flowchart</div>

#### Silent Rejection

When invoked on lanes indicating a transient state (DPInit, DPDeinit, DPTxTurnOn, DPTxTurnOff) the module may ignore Apply triggers; the result is then undetermined in general.

Modules should preferably provide rejection feedback (ConfigRejected)

| Step | Action | Who Performs? |
|------|--------|---------------|
| Definition | Write desired settings into Staged Control Set | Host |
| Apply Trigger | Host writes lane selection bit-mask to ApplyDPInit or ApplyImmediate register, triggering the provisioning process. | Host (Trigger) → Module (acceptance) |
| Provisioning (Execution) | Validates and copies settings from Staged to Active Control Set. Set DPInitPending. Does not yet apply to hardware | Module |
| Commissioning (Execution) | Commit settings from Active Control Set to hardware, either automatically or explicitly initiated, depending on trigger used and procedure type (See Table 16) | Module |
| Result Reporting | Update per-lane ConfigStatus (either ConfigSuccess or ConfigRejected) | Module |

**Table 15 Control Set Configuration Procedures**

- Staged Control Set 0, Apply Triggers: Table 8-72 (Page 10h, Bytes 145-152, OIF-CMIS-05.3)
- Staged Control Set 1, Apply Triggers: Table 8-77 (Page 10h, Bytes 180-187, OIF-CMIS-05.3)
- ConfigStatus Register Table 8-91 (Page 11h, Bytes 202-205, OIF-CMIS-05.3)

| Procedure Type | DPSM States Allowed | Provisioning | Commissioning | DPSM Impact | Host intervention needed? |
|----------------|---------------------|--------------|---------------|-------------|---------------------------|
| Stepwise (Provision only) | DPDeactivated | Explicitly triggered by host | Host explicitly initiates; module then executes commissioning | DPSM transitions explicitly controlled by host (DPDeactivated → DPInit) | Yes |
| Intervention-free Regular (Provision + Commission) | DPActivated or DPInitialized | Triggered by ApplyDPInit | Automatic commissioning executed by module via DPSM state cycling (DPDeactivated → DPInit) | DPSM state automatically cycled by module | No (automatic) |
| Intervention-free Hot (Provision + Commission) | DPActivated or DPInitialized | Triggered by ApplyImmediate | Automatic commissioning executed immediately by module without DPSM transitions | No DPSM transitions; immediate commit | No (automatic, fastest) |

**Table 16 Procedure Type**

![image](https://hackmd.io/_uploads/rJbYFEa9gg.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 18 Provisioning Process</div>

![image](https://hackmd.io/_uploads/SklLKFVp9xl.png)

<div style="text-align: center; font-size: 12px; font-weight: bold;">Figure 19 Commissioning Process</div>

---

:::info
**Data path state change flags Behavior and its relation to the below sub sections:**
- Module Flag Conformance Rules
- Lane-Specific Flagging Conformance Rules  
- VDM Flagging Conformance per Stat
:::