### 第三組
### 第二次作業報告
410786004 蘇家駒
410785031 黃駿朋
410785040 林嘉昱
410786018 林家均
410786029 林韋廷
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#### 2.18 ) Assume that we would like to expand the MIPS register file to 128 registers and expand the instruction set to contain four times as many instructions.
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#### 2.18.1 ) How would this affect the size of each of the bit fields in the R-type instructions?
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we know **R-type** :
| opcode | rs | rt | rd | shamt | funct |
| ---------- | ---------- | ---------- | ---------- | ---------- | ---------- |
| $6 \ bits$ | $5 \ bits$ | $5 \ bits$ | $5 \ bits$ | $5 \ bits$ | $6 \ bits$ |
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***opcode :***
Because expanded $\ 2^2$ times.
$\implies$ add $\ 2\ bits$.
$\implies \ 6+2=8 \ bits$ for $opcode$.
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***rs, rt, rd :***
we have $128=2^7$ registers.
$\implies \ 7 \ bits$ for $rs,\ rt,\ rd$.
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***shamt, funct :***
$32 - 8 - 7 \times 3 = 3 \ bits$ for $shamt,\ funct$.
we can choose $shamt \ 2 \ bits, \ funct \ 1 \ bits$ or $shamt \ 1 \ bits, \ funct \ 2 \ bits$.
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### **Answer**
| opcode | rs | rt | rd | shamt | funct |
| ---------- | ---------- | ---------- | ---------- | ---------- | ---------- |
| $8 \ bits$ | $7 \ bits$ | $7 \ bits$ | $7 \ bits$ | $2 \ bits$ | $1 \ bits$ |
or
| opcode | rs | rt | rd | shamt | funct |
| ---------- | ---------- | ---------- | ---------- | ---------- | ---------- |
| $8 \ bits$ | $7 \ bits$ | $7 \ bits$ | $7 \ bits$ | $1 \ bits$ | $2 \ bits$ |
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#### 2.18.2 ) How about the change in the I-type instructions?
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we know **I-type** :
| opcode | rs | rt | constant or address |
| ---------- | ---------- | ---------- | ------------------- |
| $6 \ bits$ | $5 \ bits$ | $5 \ bits$ | $16 \ bits$ |
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***opcode :***
Because expanded $\ 2^2$ times.
$\implies$ add $\ 2\ bits$.
$\implies \ 6+2=8 \ bits$ for $opcode$.
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***rs, rt :***
we have $128=2^7$ registers.
$\implies \ 7 \ bits$ for $rs,\ rt$.
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***constant, address :***
$32 - 8 - 7 \times 2 = 10 \ bits$ for $constant \ or \ address$.
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### **Answer**
| opcode | rs | rt | constant or address |
| ---------- | ---------- | ---------- | ------------------- |
| $8 \ bits$ | $7 \ bits$ | $7 \ bits$ | $10 \ bits$ |
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#### 2.18.3 ) How could each of the two proposed changes decrease the size of an MIPS assembly program? On the other hand, how could the proposed change increase the size of an MIPS assembly program?
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### **Answer**
1. Because instruction set is expanded, we can use more function to simplify our program. For example, we can define function ***swap*** to deal with data exchange which takes 3 instructions before.
2. In $question\ 1$, we see that $shamt$ field decreased, which means that we should take more ***shifting function***. For example, instead of writing ***"sll $s0, 16"***, we would need to write ***"sll $s0, 1"*** $16$ times.
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#### 2.47 ) Assume a program :
| arithmetic | load/store | branch |
| ---------- | ---------- | -------- |
| 70% | 10% | 20% |
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#### 2.47.1 ) Find the average CPI.
| arithmetic | load/store | branch |
| ---------- | ---------- | -------- |
| 2 cycles | 6 cycles | 3 cycles |
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### **Answer**
| arithmetic | load/store | branch |
| ---------- | ---------- | -------- |
| 2 cycles | 6 cycles | 3 cycles |
| 70% | 10% | 20% |
$CPI = 0.7 \times 2 + 0.1 \times 6 + 0.2 \times 3=2.6$
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#### 2.47.2 ) For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
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### **Answer**
1. $2.6 \times 0.75 = 0.7 \times X + 1.2$
$\implies \frac{3.9}{2}-1.2=0.7X$
$\implies X=\frac{0.75}{0.7}=1.07$
$\implies$ the CPI of arithmetic instruction is $\ 1.07$.
2. $\dfrac{2-1.07}{2}=0.465$
$\implies\ 46.5\%$ improvement in arithmetic instruction.
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#### 2.47.3 ) For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all?
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### **Answer**
1. $2.6 \times 0.5 = 0.7X + 1.2$
$\implies 1.3 - 1.2 = 0.7X$
$\implies X = \frac{0.1}{0.7} = 0.1428$
$\implies$ the CPI of arithmetic instruction is $\ 0.1428$.
2. $\dfrac{2-0.1428}{2}=0.928$
$\implies\ 92.8\%$ improvement in arithmetic instruction.
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