# Lab 9
Name: G Jaswanth
Roll No.: CS22B020

---
## Question 1

**Verilog Code**

module ALU(input [1:0] operand1, // 2-bit input operand 1
           input [1:0] operand2, // 2-bit input operand 2
           input [1:0] control,  // 2-bit control signal
           output reg [1:0] result); // 2-bit output result

   always @(*) begin
      case(control)
         2'b00: result = operand1 + operand2; // Addition
         2'b01: result = operand1 - operand2; // Subtraction
         2'b10: result = operand1 & operand2; // Logical AND
         2'b11: result = operand1 | operand2; // Logical OR
         default: result = 2'b00; // Default case
      endcase
   end

endmodule

module MUX4to1(input [3:0] data, // 4-bit input data
               input [1:0] select, // 2-bit select signal
               output reg out); // Output

   always @(*) begin
      case(select)
         2'b00: out = data[0];
         2'b01: out = data[1];
         2'b10: out = data[2];
         2'b11: out = data[3];
         default: out = 1'b0; // Default case
      endcase
   end

endmodule

module ALU_with_MUX(input [1:0] operand1, // 2-bit input operand 1
                    input [1:0] operand2, // 2-bit input operand 2
                    input [1:0] control, // 2-bit control signal
                    output reg [1:0] result); // 2-bit output result

   wire [1:0] alu_output;
   ALU ALU_inst(.operand1(operand1), .operand2(operand2), .control(control), .result(alu_output));

   wire [3:0] mux_input;
   assign mux_input = {alu_output, 2'b00}; // Concatenate ALU output with 2'b00 for MUX input

   wire [1:0] select_lines;
   assign select_lines = control; // Use control signal as select lines for MUX

   MUX4to1 MUX_inst(.data(mux_input), .select(select_lines), .out(result));

endmodule

---
## Question 2
**Verilog Code**

module SimpleProcessor(
    input [7:0] instruction, // 8-bit instruction
    input [7:0] data_in,     // 8-bit data input for store operation
    output reg [7:0] data_out // 8-bit data output for load operation
);

    reg [7:0] memory [0:255]; // Memory array with 256 8-bit locations
    reg [7:0] R[1:2];         // Registers R1 and R2
    
    // Instruction decoding
    reg [7:0] opcode;
    reg [7:0] dest_reg;
    reg [2:0] offset;
    reg [1:0] src_reg;
    
    // Extracting fields from instruction
    always @(*) begin
        opcode = instruction[7:6];
        dest_reg = instruction[5:4];
        offset = instruction[3:1];
        src_reg = instruction[0];
    end
    
    // Load operation
    always @(posedge src_reg) begin
        if (opcode == 2'b00) // Load instruction
            data_out = memory[R[src_reg] + offset];
    end
    
    // Store operation
    always @(posedge src_reg) begin
        if (opcode == 2'b01) // Store instruction
            memory[R[src_reg] + offset] <= data_in;
    end

endmodule

---
## Question 3

**C Code**

#include <stdio.h>

int main() {
    int num1 = 10; // Assume a random first number
    int num2 = 5; // Assume a random second number
    int sum, product;

    // Calculate sum and product
    sum = num1 + num2;
    product = num1 * num2;

    // Print the results
    printf("Sum: %d\n", sum);
    printf("Product: %d\n", product);

    return 0;
}

### output: