# Debug in Caraval-SoC by James Sa ----  ---- Pragmatic Keyboard  Note: I have been a software engineer for 20+ years, with a particular interest in Bluetooth and keyboard design for the past 4 years. ---- ### Why this course? I made some of devboard for AVR, STM32 for work and fun. 想要了解更多。 ### What do I learn so far? Caraval SoC project, hardware design toolchain. ### What support do I nee?d 其實我不知道我會在本報告中以我自己的角度-硬體設計初學者-來分享，然後請大家告訴我該如何進步。 40歲才開始自主學習 --- # caravel-soc testbench ---- ## run_sim ```verilog [4] ## Mgmt Core Wrapper -v ../../rtl/soc/mgmt_core.v -v ../../rtl/soc/mgmt_core_wrapper.v -v ../../rtl/soc/VexRiscv_MinDebugCache.v ``` [caravel-soc/testbench/counter_wb/include.rtl.list#L20](https://github.com/bol-edu/caravel-soc/blob/0adf2100995dcd24abef1da1ffd4deec2234bca0/testbench/counter_wb/include.rtl.list#L20) Note: 不懂就問助教，感謝Kevin花時間解答。官方預設是用MinDebugCache，但我們嘗試要搭配使用gdb debugging時發現MinDebugCache不支援 只有minDebug支援，所以run debug時會用minDebug。 因為GDBWave支援simple bus。 ---- ## run_debug ```shell [1] sed -i 's/VexRiscv_MinDebugCache.v/VexRiscv_MinDebug.v/' ./include.rtl.list cp ../gdbwave.make ./Makefile make vcd2fst counter_wb.vcd counter_wb.fst mv counter_wb.fst waves.fst ``` [caravel-soc/testbench/counter_wb/run_debug#L28](https://github.com/bol-edu/caravel-soc/blob/0adf2100995dcd24abef1da1ffd4deec2234bca0/testbench/counter_wb/run_debug#L28) Note: 注意這兩個地方用的VexRiscv是不同的。 ---- ## diff ```diff 84c88,96 < wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; --- > wire IBusCachedPlugin_cache_io_flush; ``` Note: 如果直接去比較這兩個檔案，會發現有差別的地方其實是bus plugin。這給了我們一些線索 ---- ChatGPT 說 這兩個檔案 VexRiscvMinDebug.v 與 VexRiscvMinDebugCache.v 是位於 caravel-soc 專案中的 Verilog 硬體描述語言 (HDL) 檔案，用於實現 VexRiscv 處理器的不同版本。 主要的區別如下： 1. 功能：VexRiscvMinDebug.v 實現了 VexRiscv 處理器的最小除錯版本，提供了基本的處理器功能，例如指令執行、資料存取、暫存器等，但未包含高級功能如指令快取 (instruction cache) 和資料快取 (data cache)。而VexRiscvMinDebugCache.v 則是在 VexRiscvMinDebug.v 的基礎上，加入了指令快取 (instruction cache) 功能，可以提供更高的指令執行效能。 2. 架構：VexRiscvMinDebugCache.v 比 VexRiscvMinDebug.v 多了與指令快取相關的元件，例如 ICache 和 BMB 等，用於實現指令快取的讀取和寫入操作。 3. 效能：由於 VexRiscvMinDebugCache.v 具有指令快取功能，因此在執行指令時可以提供更高的效能，減少對外部指令存取的次數，從而提高處理器的整體效能。而 VexRiscvMinDebug.v 則僅提供基本的處理器功能，效能可能相對較低。 4. 設定：VexRiscvMinDebug.v 和 VexRiscvMinDebugCache.v 可以根據特定需求進行設定，例如指令快取的大小、寫回策略、快取行為等，以適應不同的應用場景。 總之，VexRiscvMinDebug.v 與 VexRiscvMinDebugCache.v 分別是 caravel-soc 專案中 VexRiscv 處理器的不同版本，其中 VexRiscvMinDebugCache.v 比 VexRiscvMinDebug.v 多了指令快取功能，提供了更高的效能，但可能需要更多的硬體資源。 Note: ChatGPT講的有對有錯，其實跟人一樣。其實human errs but less and less. 每次在解決問題的時候，我發現要往下一層走問題就會變得很好解決。如果停留在同一層就看不到問題的盲點。 --- # caravel management soc https://github.com/efabless/caravel_mgmt_soc_litex ---- ```python [5] if cpu == 'vexriscv': SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type="vexriscv", cpu_variant="minimal+debug", # cpu_variant="lite+debug", # cpu_reset_address=self.mem_map["flash"], cpu_reset_address=0x10000000, csr_data_width=32, ``` [caravel_mgmt_soc_litex/caravel.py#L64]( https://github.com/efabless/caravel_mgmt_soc_litex/blob/453e4cca7d165db005492cd1a93a3a8aed710e2b/litex/caravel.py#L64) ---- ```python [2] # Add Debug Interface (UART) dbg_uart = Record([('rx',1),('tx',1)]) self.submodules.dbg_uart = UARTWishboneBridge( dbg_uart, sys_clk_freq, baudrate=115200) self.add_wb_master(self.dbg_uart.wishbone) ``` [caravel_mgmt_soc_litex/caravel.py#L219]( https://github.com/efabless/caravel_mgmt_soc_litex/blob/453e4cca7d165db005492cd1a93a3a8aed710e2b/litex/caravel.py#L219) Note: Baud rate 115,200 ---- # Manual Debug support is enabled in the core and can be accessed through a dedicated UART port configured as a wishbone master. The baud rate for the port is **9600**. Note: 在前幾次同學的分享裡面，提到verilog裡面有奇怪的10進位碼，所以開始找尋這個檔案是從何而來的。note baud rate 9600，基本上這行做久了，你會知道千萬不要相信文件。 ---- trust no comment ```python [7] # Add Debug Interface (UART) dbg_uart = Record([('rx',1),('tx',1)]) self.submodules.dbg_uart = UARTWishboneBridge( dbg_uart, sys_clk_freq, baudrate=115200) self.add_wb_master(self.dbg_uart.wishbone) ``` [caravel_mgmt_soc_litex/caravel.py#L219]( https://github.com/efabless/caravel_mgmt_soc_litex/blob/453e4cca7d165db005492cd1a93a3a8aed710e2b/litex/caravel.py#L219) Note: Baud rate 115,200 ---- System UART and Debug UART是共用的 ```python [2,7] # Add System UART sys_uart = Record([('rx', 1), ('tx', 1)]) self.submodules.uart_phy = UARTPHY(sys_uart, sys_clk_freq, baudrate = 9600) self.submodules.uart = UART(self.uart_phy, tx_fifo_depth = 16, rx_fifo_depth = 16) self.irq.add("uart", use_loc_if_exists=True) # Add Debug Interface (UART) dbg_uart = Record([('rx',1),('tx',1)]) self.submodules.dbg_uart = UARTWishboneBridge(dbg_uart, sys_clk_freq, baudrate=115200) self.add_wb_master(self.dbg_uart.wishbone) ``` [caravel_mgmt_soc_litex/caravel.py#L224]( https://github.com/efabless/caravel_mgmt_soc_litex/blob/453e4cca7d165db005492cd1a93a3a8aed710e2b/litex/caravel.py#L224) Note: System UART and Debug UART是共用的 Debug support is enabled in the core and can be accessed through a dedicated UART port configured as a wishbone master. The baud rate for the port is 9600. ---- caravel_mgmt_soc_litex/verilog/rtl/ ``` VexRiscv_LiteDebug.v VexRiscv_MinDebug.v VexRiscv_MinDebugCache.v ``` Note: 其實可以找到三個.v，這我又不理解為什麼了。 --- # Litex ----  ---- ```python [3] CPU_VARIANTS = { "minimal": "VexRiscv_Min", "minimal+debug": "VexRiscv_MinDebug", "minimal+debug+hwbp": "VexRiscv_MinDebugHwBP", "lite": "VexRiscv_Lite", "lite+debug": "VexRiscv_LiteDebug", "lite+debug+hwbp": "VexRiscv_LiteDebugHwBP", "standard": "VexRiscv", "standard+debug": "VexRiscv_Debug", ``` [https://github.com/enjoy-digital/litexsoc/cores/cpu/vexriscv/core.py#L30](https://github.com/enjoy-digital/litex/blob/b367c27191511f36b10ec4103198978f86f9502c/litex/soc/cores/cpu/vexriscv/core.py#L30) ----  Note: https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC ---- ```python def add_debug(self): debug_reset = Signal() ibus_err = Signal() dbus_err = Signal() self.i_cmd_valid = Signal() self.i_cmd_payload_wr = Signal() self.i_cmd_payload_address = Signal(8) self.i_cmd_payload_data = Signal(32) self.o_cmd_ready = Signal() self.o_rsp_data = Signal(32) self.o_resetOut = Signal() ``` [https://github.com/enjoy-digital/litex/soc/cores/cpu/vexriscv/core.py#L196](https://github.com/enjoy-digital/litex/blob/b367c27191511f36b10ec4103198978f86f9502c/litex/soc/cores/cpu/vexriscv/core.py#L196) --- # Vex Risc V ---- MinDebug系列 ```text minDebug IBusSimplePlugin simple and neutral memory interface going outside the CPU. https://github.com/SpinalHDL/VexRiscv#ibussimpleplugin DBusSimplePlugin This plugin implements the load and store instructions (LB/LH/LW/LBU/LHU/LWU/SB/SH/SW) via a simple memory bus going out of the CPU. https://github.com/SpinalHDL/VexRiscv#dbussimpleplugin ``` ---- MinDebugCache系列 ```text minDebugCache Simple and light multi-way instruction cache https://github.com/SpinalHDL/VexRiscv#ibuscachedplugin DBusCachedPlugin Multi way cache implementation with writh-through and allocate on read strategy. https://github.com/SpinalHDL/VexRiscv#dbuscachedplugin ``` ---- ```text [3,8] caravel-soc/rtl/soc/VexRiscv_MinDebug.v BranchPlugin, CsrPlugin, DBusSimplePlugin, DebugPlugin, HazardSimplePlugin, IBusSimplePlugin, IntAluPlugin, LightShifterPlugin, RegFilePlugin, ShiftPlugin, SrcPlugin caravel-soc/rtl/soc/VexRiscv_MinDebugCache.v BranchPlugin, CsrPlugin, DBusSimplePlugin, DebugPlugin, HazardSimplePlugin, IBusCachedPlugin, IntAluPlugin, LightShifterPlugin, RegFilePlugin, ShiftPlugin, SrcPlugin ``` 原來Cache指的是IBusCachedPlugin. Note: 我找了好多天都找不到這顆CPU的定義檔，所以一個寫了一個Python Script把verilog裡面的Plugin都找出來。 --- # GDBWave Note: Demo gdb remote with GDBWave. ----  ---- GDBWave currently only works with CPUs that have a single instruction, in-order execution pipeline. It’s not difficult to extend GDBWave support to more complex CPU architectures, but that’s outside the scope of this Christmas holiday project. --- # Bonus ---- macOS的環境設定 ```shell $ brew tap riscv-software-src/riscv $ brew install riscv-tools gtkwave icarus-verilog ``` ---- GDB remote serial protocol  ---- Stepi command