---
# System prepended metadata

title: LAB-9

---

# Lab 9

**Name :- Viramgama Jaimin Piyushbhai
Roll No.:- CS22B051**

---
## Question 1
**Verilog Code**
```verilog=
module ALU(input [1:0] a, input [1:0]b, output [3:0]ans, output[1:0] ctr);
    // 4_to_1 MUX design 
    always @*
    begin
    case(ctr)
        2'b00 : assign ans = a + b; // Addition
        2'b01 : assign ans = a - b; // Subtraction
        2'b10 : assign ans = a & b; // Logical AND
        2'b11 : assign ans = a | b; // Logical OR
    endcase
    end
endmodule 
```
**TestBench**
```verilog=
module ALU_tb;
    reg [1:0] operand1;
    reg [1:0] operand2;
    reg [1:0] control;
    wire [3:0] result;
    
    ALU inst(.a(operand1), .b(operand2), .ans(result), .ctr(control));
    
    initial begin
    // Test case 1: Addition
    operand1 = 2'b10;
    operand2 = 2'b01;
    control = 2'b00; 
    #10;     
    
    // Test case 2: Subtraction
    operand1 = 2'b10;
    operand2 = 2'b01;
    control = 2'b01; // Subtraction
    #10;
    
    // Test case 3: Logical AND
    operand1 = 2'b10;
    operand2 = 2'b01;
    control = 2'b10; // Logical AND
    #10;
        
    // Test case 4: Logical OR
    operand1 = 2'b10;
    operand2 = 2'b01;
    control = 2'b11; // Logical OR
    #10;
    end
    
endmodule
```
---

## Question 2
**Verilog Code**
```verilog=
module processor(input [7:0] instr);
    
    reg [7:0] memory [255:0]; // 256 bytes of memory
    reg [7:0] regis [15:0]; // 16 general 8-bit registers
    
    wire op;     // Operation
    wire [1:0] des;  // Destination register
    wire [2:0] offset; // Offset
    wire [1:0] r1;  // Address register
    
    assign op = instr[7];
    assign des  = instr[6:5];
    assign offset = instr[4:2];
    assign r1  = instr[1:0];
    
    always @(*) begin
        if (op == 1'b0) // lw operation
        begin 
            regis[des] = memory[regis[r1] + offset];
        end
        else if (op == 1'b1) // sw operation
        begin 
            memory[regis[r1] + offset] = regis[des];
        end
    end
    
endmodule
```

**TestBench**
```verilog=
module processor_tb;

    reg [7:0] instr;
    
    processor dut(.instr(instr));

    initial begin
        memory[0] = 8'b01010101;
        memory[1] = 8'b11001100;
        memory[2] = 8'b00110011;
        memory[3] = 8'b10101010;
        regis[0] = 8'b11110000;
        regis[1] = 8'b00001111;
        regis[2] = 8'b01010101;
        regis[3] = 8'b10101010;
        
        // Load instruction
        instr = 8'b01001101; // lw R2, 3(R1)
        #10;
        
        // Store instruction
        instr = 8'b11001101; // sw R2, 3(R1)
        #10;
    end
    
endmodule
```

---

## Question 3
**Cpp Code**

```C++=
#include <iostream>

int main(){
    int a=3;
    int b=4;
    int c=a+b;
    return 0;
}

```

```
Commands executed: 
    ../../../pin -t obj-intel64/inscount0.so -o inscount0.log -- /home/i-apex/Desktop/a.out
    

Final Output:    
Count 1724323
```
