HDL
===
logic design
---
- multiplier
- [signed multiplier & radix-4 signed multiplier](/8zZi1bKYRgW8k8NK2sPpqA)
verilog
---
- verilog
- __
- testbench
- [tb模擬結果調色](/4tEmhnIWSNWLwRxYaOj9Fg)
- system verilog
UVM
---
- cocotb
Algorithm
---
- quantization
- arithmetic
- codic
- systolic array
- fifo
- linebuffer
- pipeline/parallel/folding/unfolding
Q&A
---
1. assign vs always case if-else: [連結](https://iter01.com/615779.html)
2. python verilog verification
- [DIP project - sobel](/cebx-NwLSia1xtHGSm9fPw)
- [data format](/mcB_P6qFQF6Cg6SigoqDXA)
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