testbench $系統任務模擬結果調色!

相信大家在做電路模擬時，常常會因為終端機顯示結果總是黑底白字，稍微跑出多一點的輸出結果，便會讓你頓時眼花撩亂。
這個時候你就會需要一些調色小技巧!
有效提升你看終端結果的效率!
舒緩眼睛疼痛感!

用例：16bit加減法器為例，模擬加減法各100組pattern

IDE: VScode
Sim: icarus verilog
Git Bash Color
<file>

adder.v –-設計
adder_tb.v –-測試
include_file.v –-定義參數

調色後的效果

1. 調色盤

以下列出幾個常用的顏色(Black/Red/Green等等)，這裡把會需要的參數用`define定義，統一寫入include_file.v檔案，再用include呼叫到testbench裡面

在 testbench 中 include 檔案(include_file.v)


//adder_tb.v 's highlight code
`include "include_file.v"

在 include_file.v 中 `define color










//include_file.v 's hightlight code
// Regular Colors
`define Black   "\033[0;30m"     // Black
`define Red     "\033[0;31m"     // Red
`define Green   "\033[0;32m"     // Green
`define Yellow  "\033[0;33m"     // Yellow
`define Blue    "\033[0;34m"     // Blue
`define Purple  "\033[0;35m"     // Purple
`define Cyan    "\033[0;36m"     // Cyan
`define White   "\033[0;37m"     // White

2. 引用調色盤參數

raw


$display( "\033[0;32m\# %d	\033[0;36m\Input: \033[0;37m\a = %d, b = %d m = %b \033[0;37m\|| \033[0;35m\Output: \033[0;37m\c_out = %d s = %d oflow = %b",$realtime, a, b, m, c_out, s ,oflow);

evoluation


$display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);

task任務

$display 爆破展開




//example code
task display;
    $display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);
endtask

$write 利用 $write 加入 "\n" 彈性調整換行










//example code
task display;
    begin
    $write(  `Green, "# %d",$realtime);
    $write(   `Cyan, "\tInput: ");
    $write(  `White, "a = %d b = %d m = %b\t", a, b, m);
    $write( `Purple, "Output: ");
    $write(  `White, "c_out = %d s = %d oflow = %b \n", c_out, s ,oflow);
    end
endtask

將 task 放入 initial 執行




//example code
initial begin
   display;
end

完整code

adder.v


    
      
        
  
    
    

        


  


  
        
          
          module HA(carry, sum, a, b);
        
        
          
          input 	a, b;
        
        
          
          output 	sum, carry;
        
        
          
          xor A1(sum,a,b);
        
        
          
          and A2(carry,a,b);
        
        
          
          endmodule
        
        
          
          

        
        
          
          module FA(cout, sum, a, b, cin);
        
        
          
          input 	a, b, cin;
        
        
          
          output 	sum, cout;
        
        
          
          wire 	w1, w2, w3;
        
        
          
          HA g1(w2, w1, a, b);
        
        
          
          HA g2(w3, sum, w1, cin);
        
        
          
          or g3(cout, w2, w3);
        
        
          
          endmodule
        
        
          
          

        
        
          
          module adder(a, b, m, s, c_out, oflow);
        
        
          
          input 			m;
        
        
          
          input 	[15:0]	a, b;
        
        
          
          output 			oflow, c_out;
        
        
          
          output 	[15:0]	s;
        
        
          
          wire 	[14:0]	w;
        
        
          
          wire 	[15:0]	d;
        
        
          
          

        
        
          
          xor g0 (  d[0], m, b[0]  );
        
        
          
          xor g1 (  d[1], m, b[1]  );
        
        
          
          xor g2 (  d[2], m, b[2]  );
        
        
          
          xor g3 (  d[3], m, b[3]  );
        
        
          
          xor g4 (  d[4], m, b[4]  );
        
        
          
          xor g5 (  d[5], m, b[5]  );
        
        
          
          xor g6 (  d[6], m, b[6]  );
        
        
          
          xor g7 (  d[7], m, b[7]  );
        
        
          
          xor g8 (  d[8], m, b[8]  );
        
        
          
          xor g9 (  d[9], m, b[9]  );
        
        
          
          xor g10( d[10], m, b[10] );
        
        
          
          xor g11( d[11], m, b[11] );
        
        
          
          xor g12( d[12], m, b[12] );
        
        
          
          xor g13( d[13], m, b[13] );
        
        
          
          xor g14( d[14], m, b[14] );
        
        
          
          xor g15( d[15], m, b[15] );
        
        
          
          

        
        
          
          FA h0 (  w[0], s[0],  a[0],  d[0],  m    );
        
        
          
          FA h1 (  w[1], s[1],  a[1],  d[1],  w[0] );
        
        
          
          FA h2 (  w[2], s[2],  a[2],  d[2],  w[1] );
        
        
          
          FA h3 (  w[3], s[3],  a[3],  d[3],  w[2] );
        
        
          
          FA h4 (  w[4], s[4],  a[4],  d[4],  w[3] );
        
        
          
          FA h5 (  w[5], s[5],  a[5],  d[5],  w[4] );
        
        
          
          FA h6 (  w[6], s[6],  a[6],  d[6],  w[5] );
        
        
          
          FA h7 (  w[7], s[7],  a[7],  d[7],  w[6] );
        
        
          
          FA h8 (  w[8], s[8],  a[8],  d[8],  w[7] );
        
        
          
          FA h9 (  w[9], s[9],  a[9],  d[9],  w[8] );
        
        
          
          FA h10( w[10], s[10],a[10], d[10],  w[9] );
        
        
          
          FA h11( w[11], s[11],a[11], d[11], w[10] );
        
        
          
          FA h12( w[12], s[12],a[12], d[12], w[11] );
        
        
          
          FA h13( w[13], s[13],a[13], d[13], w[12] );
        
        
          
          FA h14( w[14], s[14],a[14], d[14], w[13] );
        
        
          
          FA h15( c_out, s[15],a[15], d[15], w[14] );
        
        
          
          

        
        
          
          xor j( oflow, w[14], c_out);
        
        
          
          

        
        
          
          endmodule
        
  



    

  


      
      
        view raw
        
          adder.v
        
        hosted with ❤ by GitHub

adder_tb.v


    
      
        
  
    
    

        


  


  
        
          
          `timescale 1 ns/1 ns
        
        
          
          `include "include_file.v"
        
        
          
          

        
        
          
          // a, b ,s reg signed
        
        
          
          module adder_tb();
        
        
          
           
        
        
          
          	reg 			m;
        
        
          
          	reg signed		[15:0]a, b;
        
        
          
          	wire 			oflow, c_out;
        
        
          
          	wire signed		[15:0]s;
        
        
          
          	reg 			clk;
        
        
          
          

        
        
          
          	integer 	k, test_num = 101;
        
        
          
          	integer     handle;
        
        
          
          	integer 	seed;
        
        
          
          

        
        
          
          //seed
        
        
          
          //student id 0~50, in fact it's a random seed
        
        
          
          	initial begin seed = `student_id; end                                            
        
        
          
          

        
        
          
          //m (mode) signal
        
        
          
          //`ADD m=0 , SUB m=1
        
        
          
          	initial m = `ADD;                                                         
        
        
          
          

        
        
          
          //under testing
        
        
          
              adder a1( .a(a), .b(b), .m(m), .c_out(c_out), .oflow(oflow), .s(s) );   
        
        
          
          	//adder a1( a, b, m, s, c_out, oflow );
        
        
          
          

        
        
          
          //clk signal
        
        
          
              initial clk = 0;
        
        
          
              always  #(`period/2) clk = ~clk;
        
        
          
          

        
        
          
          //a, b, cin, m signal
        
        
          
          	initial begin
        
        
          
          		//handle = $fopen("results.txt");  //uncomment  both handle and the the following $fdisplay to write to file
        
        
          
          		a <= 0;b <= 0;
        
        
          
          

        
        
          
                  for(k = 0;k < test_num; k = k + 1) begin
        
        
          
                    @(negedge clk)	
        
        
          
          			a <= $random(seed)%`rm_value;b <= $random(seed)%`rm_value;	
        
        
          
          			//$fdisplay( handle,"# %d	Input: a = %d, b = %d m = %b || Output: c_out = %d s = %d ",$realtime, a, b, m, c_out, s );
        
        
          
          			display1;
        
        
          
          

        
        
          
          		end
        
        
          
          		#(`period);
        
        
          
          		$finish;
        
        
          
          	end
        
        
          
          

        
        
          
          //waveform
        
        
          
              initial begin
        
        
          
                  $dumpfile("adder.vcd");
        
        
          
                  $dumpvars; 
        
        
          
              end
        
        
          
          

        
        
          
          //task display
        
        
          
          

        
        
          
          //Display : #    time    Input: a = _  b = _ m = _  Output: c_out = _____ s = _ oflow = _____
        
        
          
          //Module  : $realtime               a      b     m                  c_out     s         oflow 
        
        
          
          //DataType:        %d              %d     %d    %b                     %d    %d            %d   
        
        
          
          

        
        
          
          task display1;
        
        
          
              begin
        
        
          
              $write(  `Green, "# %d",$realtime);
        
        
          
              $write(   `Cyan, "\tInput: ");
        
        
          
              $write(  `White, "a = %d b = %d m = %b\t", a, b, m);
        
        
          
              $write( `Purple, "Output: ");
        
        
          
              $write(  `White, "c_out = %d s = %d oflow = %b \n", c_out, s ,oflow);
        
        
          
              end
        
        
          
          endtask
        
        
          
          

        
        
          
          task display2;
        
        
          
          	$display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);
        
        
          
          endtask
        
        
          
          

        
        
          
          endmodule
        
  



    

  


      
      
        view raw
        
          adder_tb.v
        
        hosted with ❤ by GitHub

include_file.v


    
      
        
  
    
    

        


  


  
        
          
          `define ADD 0
        
        
          
          `define SUB 1 
        
        
          
          `define rm_value 32768
        
        
          
          `define period 10
        
        
          
          `define student_id 20
        
        
          
          // Regular Colors
        
        
          
          `define Black   "\033[0;30m"        // Black
        
        
          
          `define Red     "\033[0;31m"          // Red
        
        
          
          `define Green   "\033[0;32m"        // Green
        
        
          
          `define Yellow  "\033[0;33m"       // Yellow
        
        
          
          `define Blue    "\033[0;34m"         // Blue
        
        
          
          `define Purple  "\033[0;35m"       // Purple
        
        
          
          `define Cyan    "\033[0;36m"         // Cyan
        
        
          
          `define White   "\033[0;37m"        // White
        
  



    

  


      
      
        view raw
        
          include_file.v
        
        hosted with ❤ by GitHub

tags: HDL verilog testbench vscode icarus verilog

	module HA(carry, sum, a, b);
	input a, b;
	output sum, carry;
	xor A1(sum,a,b);
	and A2(carry,a,b);
	endmodule

	module FA(cout, sum, a, b, cin);
	input a, b, cin;
	output sum, cout;
	wire w1, w2, w3;
	HA g1(w2, w1, a, b);
	HA g2(w3, sum, w1, cin);
	or g3(cout, w2, w3);
	endmodule

	module adder(a, b, m, s, c_out, oflow);
	input m;
	input [15:0] a, b;
	output oflow, c_out;
	output [15:0] s;
	wire [14:0] w;
	wire [15:0] d;

	xor g0 ( d[0], m, b[0] );
	xor g1 ( d[1], m, b[1] );
	xor g2 ( d[2], m, b[2] );
	xor g3 ( d[3], m, b[3] );
	xor g4 ( d[4], m, b[4] );
	xor g5 ( d[5], m, b[5] );
	xor g6 ( d[6], m, b[6] );
	xor g7 ( d[7], m, b[7] );
	xor g8 ( d[8], m, b[8] );
	xor g9 ( d[9], m, b[9] );
	xor g10( d[10], m, b[10] );
	xor g11( d[11], m, b[11] );
	xor g12( d[12], m, b[12] );
	xor g13( d[13], m, b[13] );
	xor g14( d[14], m, b[14] );
	xor g15( d[15], m, b[15] );

	FA h0 ( w[0], s[0], a[0], d[0], m );
	FA h1 ( w[1], s[1], a[1], d[1], w[0] );
	FA h2 ( w[2], s[2], a[2], d[2], w[1] );
	FA h3 ( w[3], s[3], a[3], d[3], w[2] );
	FA h4 ( w[4], s[4], a[4], d[4], w[3] );
	FA h5 ( w[5], s[5], a[5], d[5], w[4] );
	FA h6 ( w[6], s[6], a[6], d[6], w[5] );
	FA h7 ( w[7], s[7], a[7], d[7], w[6] );
	FA h8 ( w[8], s[8], a[8], d[8], w[7] );
	FA h9 ( w[9], s[9], a[9], d[9], w[8] );
	FA h10( w[10], s[10],a[10], d[10], w[9] );
	FA h11( w[11], s[11],a[11], d[11], w[10] );
	FA h12( w[12], s[12],a[12], d[12], w[11] );
	FA h13( w[13], s[13],a[13], d[13], w[12] );
	FA h14( w[14], s[14],a[14], d[14], w[13] );
	FA h15( c_out, s[15],a[15], d[15], w[14] );

	xor j( oflow, w[14], c_out);

	endmodule

	`timescale 1 ns/1 ns
	`include "include_file.v"

	// a, b ,s reg signed
	module adder_tb();

	reg m;
	reg signed [15:0]a, b;
	wire oflow, c_out;
	wire signed [15:0]s;
	reg clk;

	integer k, test_num = 101;
	integer handle;
	integer seed;

	//seed
	//student id 0~50, in fact it's a random seed
	initial begin seed = `student_id; end

	//m (mode) signal
	//`ADD m=0 , SUB m=1
	initial m = `ADD;

	//under testing
	adder a1( .a(a), .b(b), .m(m), .c_out(c_out), .oflow(oflow), .s(s) );
	//adder a1( a, b, m, s, c_out, oflow );

	//clk signal
	initial clk = 0;
	always #(`period/2) clk = ~clk;

	//a, b, cin, m signal
	initial begin
	//handle = $fopen("results.txt"); //uncomment both handle and the the following $fdisplay to write to file
	a <= 0;b <= 0;

	for(k = 0;k < test_num; k = k + 1) begin
	@(negedge clk)
	a <= $random(seed)%`rm_value;b <= $random(seed)%`rm_value;
	//$fdisplay( handle,"# %d Input: a = %d, b = %d m = %b \|\| Output: c_out = %d s = %d ",$realtime, a, b, m, c_out, s );
	display1;

	end
	#(`period);
	$finish;
	end

	//waveform
	initial begin
	$dumpfile("adder.vcd");
	$dumpvars;
	end

	//task display

	//Display : # time Input: a = _ b = _ m = _ Output: c_out = _____ s = _ oflow = _____
	//Module : $realtime a b m c_out s oflow
	//DataType: %d %d %d %b %d %d %d

	task display1;
	begin
	$write( `Green, "# %d",$realtime);
	$write( `Cyan, "\tInput: ");
	$write( `White, "a = %d b = %d m = %b\t", a, b, m);
	$write( `Purple, "Output: ");
	$write( `White, "c_out = %d s = %d oflow = %b \n", c_out, s ,oflow);
	end
	endtask

	task display2;
	$display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);
	endtask

	endmodule

	`define ADD 0
	`define SUB 1
	`define rm_value 32768
	`define period 10
	`define student_id 20
	// Regular Colors
	`define Black "\033[0;30m" // Black
	`define Red "\033[0;31m" // Red
	`define Green "\033[0;32m" // Green
	`define Yellow "\033[0;33m" // Yellow
	`define Blue "\033[0;34m" // Blue
	`define Purple "\033[0;35m" // Purple
	`define Cyan "\033[0;36m" // Cyan
	`define White "\033[0;37m" // White

testbench $系統任務 模擬結果調色!

用例：16bit加減法器為例，模擬加減法各100組pattern

調色後的效果

1. 調色盤

2. 引用調色盤參數

raw

evoluation

task任務

完整code

Read more

TerosHDL(vscode 插件)

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testbench $系統任務模擬結果調色!