# testbench $系統任務 模擬結果調色!
*相信大家在做電路模擬時，常常會因為終端機顯示結果總是黑底白字，稍微跑出多一點的輸出結果，便會讓你頓時眼花撩亂。*
*這個時候你就會需要一些調色小技巧!*
*有效提升你看終端結果的效率!*
*舒緩眼睛疼痛感!*
## 用例：16bit加減法器為例，模擬加減法各100組pattern
:::info
IDE: VScode
Sim: icarus verilog
Git Bash Color
<file>
- adder.v ---設計
- adder_tb.v ---測試
- include_file.v ---定義參數
:::
## 調色後的效果
---
### 1. 調色盤
以下列出幾個常用的顏色(Black/Red/Green等等)，這裡把會需要的參數用`define定義，統一寫入include_file.v檔案，再用include呼叫到testbench裡面
- 在 testbench 中 include 檔案(include_file.v)
```verilog=
//adder_tb.v 's highlight code
`include "include_file.v"
```
- 在 include_file.v 中 `define color
```verilog=
//include_file.v 's hightlight code
// Regular Colors
`define Black "\033[0;30m" // Black
`define Red "\033[0;31m" // Red
`define Green "\033[0;32m" // Green
`define Yellow "\033[0;33m" // Yellow
`define Blue "\033[0;34m" // Blue
`define Purple "\033[0;35m" // Purple
`define Cyan "\033[0;36m" // Cyan
`define White "\033[0;37m" // White
```
### 2. 引用調色盤參數
#### raw
```verilog=
$display( "\033[0;32m\# %d \033[0;36m\Input: \033[0;37m\a = %d, b = %d m = %b \033[0;37m\|| \033[0;35m\Output: \033[0;37m\c_out = %d s = %d oflow = %b",$realtime, a, b, m, c_out, s ,oflow);
```
#### evoluation
```verilog=
$display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);
```
#### task任務
- $display 爆破展開
```verilog=
//example code
task display;
$display(`Green,"# %d",$realtime, `Cyan,"\tInput: ", `White, "a = %d, b = %d m = %b", a, b, m, `Purple," Output: ", `White, "c_out = %d s = %d oflow = %b", c_out, s ,oflow);
endtask
```
- $write 利用 $write 加入 "\n" 彈性調整換行
```verilog=
//example code
task display;
begin
$write( `Green, "# %d",$realtime);
$write( `Cyan, "\tInput: ");
$write( `White, "a = %d b = %d m = %b\t", a, b, m);
$write( `Purple, "Output: ");
$write( `White, "c_out = %d s = %d oflow = %b \n", c_out, s ,oflow);
end
endtask
```
- 將 task 放入 initial 執行
```verilog=
//example code
initial begin
display;
end
```
---
### 完整code
adder.v
{%gist JackyPro/b9885e883e7b9b6aab3558535e3d768e %}
adder_tb.v
{%gist JackyPro/c22749863be3654994d41afb36d992e2 %}
include_file.v
{%gist JackyPro/b8403fce393eac3b2978d6a0402c4cb6 %}
tags: `HDL` `verilog` `testbench` `vscode` `icarus verilog`
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