---
# System prepended metadata

title: verilog 除法討論

---

# verilog 除法討論
### 說明
verilog只有整數除法，因此需要將要算的值縮放置整數，再進行運算。
如下範例，SF為縮放因子，將a放大SF倍，算完的c再縮小SF_倍。

---
*(若以上說明有誤，還請更正)*
```verilog=
// file: calculate.v
module test();
    reg signed [63:0] a;
    reg signed [63:0] b;
    reg signed [127:0]c;
    real a_fp, b_fp;
    real c_fp;
    //integer a, b;
    //integer c;
    real SF  = 100000000;
    real SF_ = 0.00000001;
initial begin
    a    = -2*SF;  b    = 910;
    a_fp = -2*SF;  b_fp = 910;
    c    = a/b;
    c_fp = a_fp/b_fp;
    $display("[verilog]\ta: %10d b: %10d c: %10.10f", a, b, c*SF_);
    $display("[fp     ]\ta: %10d b: %10d c: %10.10f", a_fp, b_fp, c_fp*SF_);
end
endmodule
```
![](https://i.imgur.com/nJRxXyP.png)


