# LEO'S HOME PAGE
## BRIEF INTRO.
Hi there! I'm Leo. Welcome to my personal website, I built this website mainly for **job/intern** application. I'm looking forward to any job/intern openings related to **digital IC design**.
Hope you find me competent for your job/intern openings! Feel free to contact me via the contact column written below for further scheduling.
## EDUCATION
- September 2019 - 2023
National Cheng Kung University, Tainan, Taiwan
B.S., Mechanical Engineering (ME)
- September 2021 - 2023
Since I discovered my real interest is in electrical engineering(EE) in my sophomore, I started to plan out my curriculum.
Despite the 145 credits in ME department I have to take in order to graduate, I've managed to take over 50 credits in EE department by now so as to prepare myself for graduate program application.
I've been relentless in the pursuit of my goal ever since September 2021, and my goal is to be admitted to the EE graduate program at the university I have applied to.
- October 2022 - Present
My application for **pre-graduate program(預研生制度)** in the VLSI/CAD group of NCKU EE department has been successfully approved in fall semester 2022. I've been taken graduate courses since then.
>My graduate program instructor is Prof. [LIH-YIH Chiou](https://www.ee.ncku.edu.tw/teacher/index2.php?teacher_id=152).

## MAIN CHARACTER
I'm a firm believer that always give 120 percent of your effort at what you want, because if others were to dissuade you from your goal and exhaust you 20 percent of your effort, you would still have 100 percent to get after it.
> It's not over until I win.
## COURSES
### EE Basics
- Electric Circuits(1)(E221110XY) (A+)
- Electric Circuits(2)(E2211201) (A+)
- Electronics(1)(E2270101) (A+)
- Electronics(2)(E2270201) (in progress)
- Electrical Engineering Laboratory(E2114003B) (A)
- Introduction to Electrical Machinery(E2280003) (A+)
### Digital Circuit Design
- Logic System(E2164012) (A)
- Logic System Laboratory(E2116004) (A-)
- Computer Organization(E2217002) (A+)
- VLSI System Design(E242700) (A)
- Digital Signal Processing(Q355000) (A)
- FPGA Design(E236800) (A+)
### Software Programming
- Computer Program Design(E120500)
- Introduction to Computers(1)(E216610XY)
- Introduction to Computers(2)(E216620XY)
- Introduction to Data Structures(E2316011) (A-)
- Discrete Mathematics(E2405001) (A)
- Computer Algorithm(E246400) (A)
- Introduction to Theory of Computation(J020300) (A+)
### Graduate Courses
- Digital Signal Processing(Q355000) (A)
- AI-on-Chip for Machine Learning and Interface (Q362700) (A+)
- Introduction to Neural Network(N278700) (A)
- VLSI System Design(N25K300) (A+)
- Low Power System Design
- Electronic System Level Design
## SKILLS
### Programming Laguages
- SystemC
- Python
- C/C++
- Verilog/ System Verilog/ SVA(System Verilog Assertion)
- Assembly
### EDA Tools Usage
- Verdi
- JasperGold - Superlint
- JasperGold - ABVIP
- Synopsys - Design Compiler
- Spyglass - CDC
- Memory Compiler
- ICC2
## PROJECT EXPERIENCES
### RISCV-Pipelined CPU with L1-Cache
- September 2022 - January 2023.
- Working under the course - VLSI system design instructed by Prof. [Kuen-Jong Lee](https://www.ee.ncku.edu.tw/teacher/index2.php?teacher_id=45).
- RISCV-5-stage-pipeline CPU + L1Cache.
- CPU has been successfully **layout**-ed using tool **innovus**.
### Systolic array
- Febuary 2023 - June 2023.
- Working under course "AI-on-Chip for Machine Learning and Interface" instructed by Prof. [Chia-Chi Tsai](https://www.ee.ncku.edu.tw/teacher/index2.php?teacher_id=170), EE, NCKU.
- Design a 8*8 systolic array as CNN hardware accelerator.
- Deploy on PYNQ Z2 **FPGA** board.
- Skills learned:
- 1. Design **tiling loop** to optimize energy efficiency on limited device constraint.
- 2. Familiar with **Vivado**, **Vitis**.
- 3. Understand the relationship btw. PS and PL, and can manipulate them fluently on FPGA.
- [report link](https://hackmd.io/iobnIE6NRJWSMI4V18lEzQ?view#Tiling)
- FPGA utilization
### Connected Component Labeling Hardware Design
- October 2022 - January 2023.
- Working under the guidance of Prof. [Lih-Yih Chiou](https://www.ee.ncku.edu.tw/teacher/index2.php?teacher_id=152), EE, NCKU.
- Connected component labeling (CCL) algorithm is one of the indispensable algorithms in computer vision today.
- My work has been devoted to find a better algorithm that maximizes computation efficiency and minimizes memory space. Parallel implementation is favored.
- Deployed on FPGA and alreay tested the functionality of the design.
### System on Chip(SoC) with Application Specific Processor(ASP)
- September 2023 - January 2024.
- Working under course "VLSI System Design(graduate level)" instructed by Prof. [Lih-Yih Chiou](https://www.ee.ncku.edu.tw/teacher/index2.php?teacher_id=152), EE, NCKU.
- We design an Application Specific Processor(ASP) that its targeted AI model is [Unet(Segmentation CNN model)](https://link.springer.com/chapter/10.1007/978-3-319-24574-4_28).
- The ASP can compute **256 multiplications/cycle**, with **maxpooling** unit, **ReLU** unit, and **requantization** unit.
- The system has **5 clock domains** and the diagram is shown as below.
- The system can run booting programs plus various application programs on a RISCV-pipelined CPU.
- The system can inference an image successfully, the result is shown as below.
- The system is layout-ed using **ICC2**.
- Skills learned:
- 1. Integrate the designed IP with the system(DRAM, ROM, SRAM, AXI bus, Watch Dog Timer, CPU, L1-Cache, **interrupt mechanism**).
- 2. **Clock Domain Crossing**(CDC) issues hadling using CDC interface.
- 3. Design an AI accelerator and also design **tiling loop** to optimize dataflow and reduce off-chip DRAM access as much as possible.
- 4. Layout using ICC2.

## HONORS
NCKU Presidential Award/ Outstanding student for the academic achievement in the school year 2020-2021.
## ENGLISH PROFICIENCY
### TOEIC
- 890/990 / Golden Certificate @Feb. 2019
- 970/990 / Golden Certificate @Aug. 2022
## CONTACT
### Email
[e-mail]
### Links
[LinkedIn](https://www.linkedin.com/in/leo-tsai-2255a3246/)
[104](https://profile.104.com.tw/5dksNt71GHH/about/edit)