---
description: In this lab, we are going to talk about sequential logic, and the meaning of memory elements in our designs, which is one of the most important concepts in logic design which will allow us to make our design remember.
---
<h1 style='border: none'><center>Digital Design Lab 8</center></h1>
<h2 style='border: none'><center>Introduction to Sequential Logic</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Authors: Usama R. Al Zayan and Enaam Rajab<span style="float:right">2022/11/25</span></h6>
<h6>Parts of this Lab were adapted from work done by Mohammed Nafiz ALMadhoun and Mai Z. Alyazji.</h6>

---
## Introduction

<p style='text-align:justify'>
In this lab, we are going to talk about sequential logic, and the meaning of memory elements in our designs, which is one of the most important concepts in logic design which will allow us to make our design remember.
</p>

## Introduction to Sequential Logic

As you might notice when you use your calculator or the coffee vending machine, the machine will remember your choice even after your release the buttons, this is what a memory element will enable you to do.

A memory element is something that remembers its previous state, and we can create a simple memory element using gates of course.

### SR Latch

The SR latch will enable us to set or reset it using two inputs called `S`, and `R`, and here is the truth table for it:

<style>
.markdown-body table {
margin: 0 auto 16px;
width: fit-content;
}
</style>

| S | R | Q |
|:---:|:---:|:--------------:|
| 0 | 0 | Previous State |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Invalid |

<center>

Basic SR Latch
</center>

This design will output `1` if `S=1` and `R=0`, and it will save the value `1` even if `S=0` and `R=0`, and it will output `0` if `S=0` and `R=1`, and it will output the value `0` even after we set `S=0` and `R=0`.

This is our basic **SR Latch** that enables us to store a value in it, note that no one design SR Latch using `AND`, `OR`, and `NOT` gates, we could use two gates of `NOR`, or `NAND` to achieve it.

<center>

SR Latch using NOR
</center>

**Note:** The output of the latch will be on the Reset side, the inverted output will be on the Set side.

### D-Latch

As you may notice, the design of the SR latch is kinda useless to store data, as you will have to drive the `S`, and `R` singles, but SR Latch is the basic building block for memory elements.

The D Latch has two inputs Data and Enable, the `D` input will be the data we want to store, and the `E` input will be the enabling single to store that data.

<center>

D-Latch
</center>

The truth table for the **D-Latch**, which will have two inputs `D`, and `E`, and output two singles `S`, and `R` will be:

| E | D | S | R |
|:---:|:---:|:---:|:---:|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |

which will result in a latch with this truth table:

| E | D | Q |
|:---:|:---:|:--------------:|
| 0 | 0 | Previous State |
| 0 | 1 | Previous State |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

We could design a **D-Latch** using only `NAND` gates using the following design.

<center>

D-Latch Using NANDs
</center>

<div style="page-break-after: always;"></div>

## Lab Tasks

### Task 1: Build an SR Latch

In this task, you should design an SR Latch using `NOR` gates, you should simulate it using Logisim first.

### Task 2: Convert your previous SR Latch to D-Latch

Using two`AND` gates, and an inverter build a D-Latch, you should simulate your design before building it.

## DataSheets
Please find the datasheets here:

**$74/02$** [DM74LS02 Quad 2-Input NOR Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS02_FairchildSemiconductor.pdf).
**$74/04$** [DM74LS04 Hex Inverting Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS04_FairchildSemiconductor.pdf).
**$74/08$** [DM74LS08 Quad 2-Input AND Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS08_FairchildSemiconductor.pdf).

###### tags: `Digital Design` `Digital` `IUG` `Computer Engineering`
<center>End Of Lab 8</center>