---
description: In this lab, we are going to talk more about sequential logic, we will start by builidng edge-triggered D Flip-Flop, and understand the befients from it, then we will talk about clocks, how to generate clocks and the purpose of having a clock in our system.
---
<h1 style='border: none'><center>Digital Design Lab 9</center></h1>
<h2 style='border: none'><center>Introduction to Sequential Logic II</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Authors: Usama R. Al Zayan and Enaam Rajab<span style="float:right">2022/11/25</span></h6>
<h6>Parts of this Lab were adapted from work done by Mohammed Nafiz ALMadhoun and Mai Z. Alyazji.</h6>

---

## Introduction

<p style='text-align:justify'>
In this lab, we are going to talk more about sequential logic, we will start by builidng edge-triggered D Flip-Flop, and understand the befients from it, then we will talk about clocks, how to generate clocks and the purpose of having a clock in our system.
</p>

## Flip-Flops

The problem with our prevous D-Latch is that it will pass that data if the enable line is `true`, so the flaw in this design is that we don't have a certain moment for capturing the data, which will lead to lot of problems later.

Imagine if you want to create a counter that counts from 0 to 15, you will need 4 D-Latches to save the previous data, a 4-Bits adder to add `1` to the previous value, then you will connect the output of the adder to the latch to update it.

The problem here is that if we enabled the latch we will never guess what will be stored in it, as it will update then the adder will add one then it will add agine (beacuse the enable still `1`), and so on.

<div style="page-break-after: always;"></div>

### D Flip-Flop

The solution for the above problem is that we can create a latch that only updates its value on certain edge (not level), so it will update only if the signal goes from `low` to `high` (rising edge), or from `high` to `low` (falling edge).

This device can be created easily using two latches:

<center>

D Flip-Flop
</center>

Notice that even if `C` is `1` and `D` is `1`, the output is `0`, because our flip-flop will only updates its value on the rising edge.

<center>

D Flip-Flop Digram
</center>

### Counter using Flip-Flop

You could design a 4-bit counter using 4 D Flip-Flops and 4 Full-Adders, the concept here is that you will need to add `1` to the ouptut of the flip-flops then store the output of the full-adders to the flip-flops

<center>

Counter using D Flip-Flops
</center>

**Note:** You can use register and 4-bit full-adder in Logisim.

## Clock

When we say clock in digital design, we don't mean a real time clock, we mean the basic clock, which is something that gives a meaning to time!

As you know an `AND` gate won't know anything about seconds or minutes, so we have the basic clock, which will generate a wave in a certain amount of time, we usual measure the amount of time using frequancy (how many waves in one second).

So a 1 Hz clock will generate a complate wave each second, we will use a sequare wave with 50% duty.

<center>

Sequare Wave Clocks
</center>

### Working with Clock in the Lab

In the lab, we will have a clock generator, which you can adjust the speed of it as you wish, and you also have pulse inputs, which generate a plus when you push it down.

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### Generating Clock

To generate a clock, we will use 555 timer chip, first, we will understand how this timer works, then we will talk about how to use it!

<center>

555 Timer
</center>

<p style='text-align:justify'>
At the begining our capacitor will behave as short circuit, so trigger and threshold will have <b>0 volt</b>, so the output of the threshold comparator will be <b>0</b>, and the output of the tigger comparator will be <b>1</b>, thus the output will be <b>1</b>.
</p>
<p style='text-align:justify'>
After some time, the capacitor will charge to <b>1.66 volt</b>, which will result make the trigger comparator output <b>0</b>, then it will charge to <b>3.33 volt</b>, which will make the threshold comparator output <b>1</b>, this will make our output goes high <b>1</b>, and the discharge transistor will open.
</p>
<p style='text-align:justify'>
After some time of opeining the discharge transistor, the voltage will drop below <b>3.33 volt</b>, which will make threshold comparator output <b>0</b>, then it will drop below <b>1.66 volt</b>, which will make the trigger output <b>1</b>, which will set our latch output to <b>1</b>.
</p>

Then the cicule will repeat.

So as you might notice, to adjust the speed of charging and discharging we will need to adjust $R_A$ and $R_B$ and $C$, if the resistors or capacitor are bigger, it will take more time to charge.

According to the datasheet to calculate the time for each wave we will use the following equation:

$T = 0.693 (R_A + 2R_B) C$

And to calculate the frequacny it will be

$f = \frac{1}{T} = \frac{1.44}{(R_A+2R_B)C}$

**Note:** There are some more pins in the chip, some of them you will not use (e.g. reset), and some have recommended capcitors and resistors (e.g 0.01μF capacitor on pin 5), which will make your output much cleaner.

<div style="page-break-after: always;"></div>

## Lab Tasks

### Task 1: Build a D Flip-Flop using D-Latch

Return to task 2 in the prvious lab to build two D-Latches, then connect them both to create a D Flip-Flop.

### Task 2: Use 74/74 Chip to create T Flip-Flop

The 74/74 Chip is a `Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs`, which mean we will have two flip-flops in this chip.

Use this chip to create to test the D Flip-Flop in it, then create a T Flip-Flop using it!

### Datasheets

- **$74/02$** [DM74LS02 Quad 2-Input NOR Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS02_FairchildSemiconductor.pdf).
- **$74/04$** [DM74LS04 Hex Inverting Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS04_FairchildSemiconductor.pdf).
- **$74/08$** [DM74LS08 Quad 2-Input AND Gates](https://cdn.datasheetspdf.com/pdf-down/7/4/L/74LS08_FairchildSemiconductor.pdf).
- **$74/74$** [DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs](https://www.futurlec.com/Datasheet/74ls/74LS74.pdf).

###### tags: `Digital Design` `Digital` `IUG` `Computer Engineering`
<center>End Of Lab 9</center>