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# System prepended metadata

title: Digital Design Lab 10
tags: [IUG, Digital Design, Computer Engineering, Digital]

---

---
title: Digital Design Lab 10

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<h1 style='border: none'><center>Digital Design Lab 10</center></h1>
<h2 style='border: none'><center>Registers & Counters</center></h2>
<h5><center>The Islamic University of Gaza<br>Engineering Faculty<br>Department of Computer Engineering</center></h5>
<h6>Authors: Usama R. Al Zayan and Enaam Rajab<span style="float:right">2022/11/25</span></h6>
<h6>Parts of this Lab were adapted from work done by Mohammed Nafiz ALMadhoun and Mai Z. Alyazji.</h6>
---

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## Introduction

<p style='text-align:justify'>
In this lab, we are going to talk about registers, then we will talk about counters, finally, we will have a state machine that we should implement the logic for it using a counter.
</p>

## Registers

A Register is just a group of flip-flops, which are connected in a certain way depending on the register type.

### n-bit register

A regular data register is just a group of flip-flops with one common clock (And control singles), so if we want to store n-bits of data, we will use an n-bit register, which contains n number of flip-flops.

<center>

![3-bit Register](https://i.imgur.com/cBcMS6v.png =300x)
3-bit Register
</center>

### Register with Parallel Load

The idea here is to modify the previous design, so we will have an extra signal `load`, the `load` will control if the register should store the data on the next clock or not.

We can simply design this register using a multiplexer.

<center>

![Register With Parallel Load](https://i.imgur.com/hqKiuGo.png =400x)
Register With Parallel Load
</center>

### Shift Register

The bits (or flip-flops) in the shift register is connected in a way that allows the bit data to move to the next bit, this operation is called shifting, you can shift the data to the right, or the left.

The idea here is that if we want to load the 8-bits in the shift register, we could use only one single data input, but we will need 8 clock pulses to load the data (which mean it's slower).

The shift registers are widely used especially in serial communication (e.g. like USB port!).

<center>

![4-bits shift register](https://i.imgur.com/bXU70eK.png =400x)
4-bits shift register
</center>

Notice that we have serial data input, and parallel data output

## Counters

In this section, we will connect the flip-flops in a way to create a counter (which will just count!).

### Ripple Counter

The idea here is to drive the bit clock using the previous bit data, as you know we will count in each bit like this `0` -> `1` -> `0`, so as you notice, we will need the falling edge to increment the next bit.

<center>

![Ripple Counter](https://i.imgur.com/GvrIzNk.png =300x)
Ripple Counter
</center>

So as you notice, each bit will be inverted in the next clock pulse, and the clock of the bit uses the next bit inverted output (Because we want the falling edge).

### Synchronous counters

The problem with the previous design is that the clock of each flip-flop is different (which will lead to some problems later).
To create a synchronous counter (synchronous means all the flip-flops change data at the same time), we will add some combinational logic to drive the flip-flops.


<center>

![Synchronous Counter](https://i.imgur.com/iCjvmRw.png =300x)
Synchronous Counter
</center>


## Lab Tasks

### Task 1: Build a Traffic Light

You should build a traffic light which has 4 states (Red, Red & Orange, Green, Orange).

Design your state machine (which has no inputs!), and then design the output logic.

To make things easier for you, use the 74/161 counter, note you can use the reset input to reset the counter!

You should first design the state machine, then you should simulate it using Logisim, finally build it and test it.

### Datasheets

- **$74/161$** [SN54/74LS161A BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS](https://www.futurlec.com/Datasheet/74ls/74LS161.pdf).


###### tags: `Digital Design` `Digital` `IUG` `Computer Engineering`
<center>End Of Lab 10</center>