---
# System prepended metadata

title: 'Assignment3 Reindeer: SoftCUP'
tags: [Computer Architecture]

---

# Assignment3 Reindeer: SoftCUP
contributed by <`joe-U16`>

###### tags: `Computer Architecture`

## Use new test case(s) for Reindeer Simulation with Verilator


## Check the generated VCD file and use GTKwave to view the waveform

## Explain the progress
### How RISC-V Compliance Tests works and why the signature should be matched.

The test framework works at several levels. At the lowest level it runs a test with a TVM on a specific configured target device and compares the test’s output test signature against the test reference signature and reports if there is any difference. A difference indicates that the target has failed that specific compliance test. It's why the signature should be mached


### Explain how Reindeer works with Verilator.

The Reindeer soft CPU uses an C++ test bench to load code/data. And for the verilator simulation The testbench will use the toolchain (objdump, readelf) to extract code/data from sections of the .elf file. The testbench will mimic the OCD bus to load the code/data into CPU's memory. Afterwards, the start-address of the .elf file ("_start" or "__start" symbol) will be passed onto the CPU, and turn the CPU into active state.

The test bench will extract the address for begin_signature and end_signature symbol. The compliance test will utilize the hold-and-load feature, abd do following:

1. Reset the CPU, put it into hold state
2. Call upon toolchain to extract code/data from the .elf file for the test case
3. Start the CPU, run for 2000 clock cycles
4. Reset the CPU, put it into hold state for the second time
5. Read the data out of the memory, and compare them against the reference signature

![](https://i.imgur.com/GTClweP.png)

### What is 2 x 2 Pipeline? How can we benefit from such pipeline design?

Reindeer's pipeline is composed of 4 stages:
* Instruction Fetch (IF)
* Instruction Decode (ID)
* Instruction Execution (IE)
* Register Write Back and Memory Access (MEM)
![](https://i.imgur.com/lup6CoP.png)
In the 2 x 2 layout, each stage is active every other clock cycle. For the even cycle, only IF and IE stages are active, while for the odd cycle, only ID and MEM stages are active. In this way, the Instruction Fetch and Memory Access always happen on different clock cycles, thus to avoid the structural hazard caused by the single port memory.




### What is “Hold and Load”? And, how the simulation does for bootstraping?

"hold and load", which brings a hardware based OCD (on-chip debugger) into the fore.
![](https://i.imgur.com/HB4t6bh.png)

The soft CPU and the OCD can share the same UART port. The RX signal goes to both the soft CPU and OCD, while the TX signal has to go through a mux. And that mux is controlled by the OCD.

After reset, the soft CPU will be put into a hold state, and it will have access to the UART TX port by default. But a valid debug frame sending from the host PC can let OCD to reconfigure the mux and switch the UART TX to OCD side, for which the memory can be accessed, and the control frames can be exchanged. A new software image can be loaded into the memory during the CPU hold state, which gives rise to the name **"hold-and-load"**.

After the memory is loaded with the new image, the OCD can setup the start-address of the CPU, and send start pulse to make the soft CPU active.

### Can you show some signals/events inside Reindeer and describe



TBD

