TY的學習筆記
===
Verilog
---
- [Verilog](https://hackmd.io/@HsuTienYao/verilog)
FPGA
---
- [FPGA](https://hackmd.io/@HsuTienYao/fpga)
Vivado
---
- [Tool Command Language](https://hackmd.io/@HsuTienYao/toolcommandlanguage)
ModelSim
---
- [Modelsim](https://hackmd.io/@HsuTienYao/modelsim)
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