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<p style="font-size: 14px;text-align:center">
The Islamic University of Gaza
</p>

<p style="font-size: 14px;text-align:center">
    Computer Architecture Lab - 2023
</p>
<p style="color:#000033;font-weight: bold;text-align:center">
   LAB (4) || Register File Design
</p>

<p style="text-align:right">
    Eng: Amal I. Mahfouz, Eng: Hassan Sammour
</p>



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<p style="font-size:20px;color:#000066;font-weight: bold;">
   Objectives
</p>

1. Design of register files, synthesis and implementation.
2. Emulation of register file performance
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<p style="font-size:20px;color:#000066;font-weight: bold;">
   Register File Design
</p>

A register file is a component of a processor that stores a small amount of data called registers, which are small, high-speed storage locations for holding data that the processor is currently using or manipulating. A register file typically consists of multiple registers that can be read from and written to in order to transfer data between different stages of a processor's pipeline.

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<p style="font-size:20px;color:#000066;font-weight: bold;">
   How does an Register File Design unit work?
</p>

1. Register File Organization:


The register file is typically organized as an array of registers, each of which is identified by a unique address or index number. For example, a 32-bit register file might contain 32 registers, each of which is 32 bits wide, and can be addressed using a 5-bit index value.

2. Register Read:


When an instruction requires the value of a register, the register file reads the value from the specified register and provides it as an output to the rest of the processor. The read operation takes place in a single clock cycle.

3. Register Write:


When an instruction needs to write a value to a register, the register file accepts the new value and updates the specified register. The write operation also takes place in a single clock cycle.

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4. Simultaneous Access:


The register file design is often optimized to allow multiple read and write operations to be performed simultaneously. For example, some designs may allow two read operations and one write operation to take place in a single clock cycle, or vice versa.

5. Address Generation:


The address of the register to be accessed is generated by the instruction decoder, which typically includes an index field that identifies the register number. This index field is used to select the appropriate register from the register file array.

6. Register File Control:


The register file design unit may include various control signals that govern the read and write operations, such as clock enable, write enable, and read enable signals. These control signals ensure that the register file operates correctly and efficiently within the processor's pipeline.


**Overall, a register file design unit provides a fast and efficient mechanism for storing and accessing data within a processor. By organizing registers in an array and providing fast read and write operations, the register file enables the processor to quickly and easily manipulate data as it executes instructions.**

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A block diagram of MIPS register file includes 32 32-bit general purpose registers

![](https://i.imgur.com/464GVgo.png)


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<p style="font-size:17px;color:#000066;font-weight: bold;">
   Input/output Descriptions:
</p>

- Read Register1 specifies which register should be read from. That register’s data should be presented on the ReadData1 output.
- Read Register2 specifies which register should be read from. That register’s data should be presented on the ReadData2 output.
- Write Register specifies which register should be written to.
- Write Data is the data that will be written to the register specified by WriteRegister. On a rising clock edge, the data will be written to the specified register.
- Write Enable, if true, will cause the WriteData to be written to the register specified by Write-Register; otherwise, WriteData will be ignored and no register will be written to.
- Clock conveys the clock signal.

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<p style="font-size:17px;color:#000066;font-weight: bold;">
   Comprison between Register File and Memory (SRAM)
</p>

![](https://i.imgur.com/WhDriXe.png)

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Here is a picture of what your register file sub circuit, symbolically, looks like. Bold labels indicate that an input/output contains more than 1 bit of data.
![](https://i.imgur.com/pcntJKb.png)

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<p style="font-size:20px;color:#000066;font-weight: bold;">
   Assignment Statements:
</p>

1. Design a 16 Register File.
2. Connect Register File in previous problem with ALU that designed in Lab 2.