# SOC Week1
## Course Plan
### 1^st^ semester
#### Objective:
+ Learn Verilog and HLS Design Implementation on FPGA and ASIC
+ Implement an User Project and Integrate it into Caravel SOC
+ Study the SOC design and emulate it in CaravelFPGA

### 2^nd^ semester
#### Objective:
+ Learn Advanced topics in IC Design, SOC chip-level design
+ Develop an Application Accelerator
+ Complete IC design flow, and be ready for tape out

## Lecture & Lab Schedule

+ Lab2 用 HLS 去做 FIR design
+ Lab3 用 Verilog 去做 FIR design
> 教授說他故意用的複雜很多、設置了一些限制。
+ Lab4 了解SOC怎麼operate
+ Lab6 Workload Optimized SOC (WLOS)
> 大多都是Software在做
+ Lab#A-lab-interrupt: interrupt service
+ Lab#B-lab-exmem: Executing function from User Project memory
+ Lab#D-lab-sdram: SDRAM controller & SDRAM device
> 了解與學會控制SDRAM，Lab2 做了 10T BRAM，這邊就是把BRAM換成SDRAM與SDRAM controller
+ Lab#E: Software Emulation-Bit Banging
> 學習如何update homework code，原本藉由enternal FTDI(USB-SPI) device接到 mprj[1-4] 來更新frimware code，但我們在remote端沒辦法去接上usb，這個lab會學到如何透過software的方式change pins來import a protocol
+
## Notes
這學期會使用兩塊FPGA
+ PYNQ-Z2
+ KV260

### Metrics to measure the FIR system
Metrics: #-of-clock* clock_period* Gate-resource (# of LUT)
+ The lower the better
+ 等同於iclab裡面performance計算