---
# System prepended metadata

title: Bypass/Decoupling Capacitor
tags: [Circuit Design, Capacitor]

---

---
title: Bypass/Decoupling Capacitor
---
###### tags:  A Journey Through Electronics
 

# Bypass/Decoupling Capacitor

## What is a bypass capacitor?
When placing IC on a PCB, it is common to see one or multiple capacitors placing close to the IC and connected to its power pin. These capacitors are called ==bypass== or ==decoupling== capacitors.
![image](https://hackmd.io/_uploads/Sk4SH8fDgl.png)


## Why we need it?
Quick answers:
1. Noise suppression
2. Local energy reservoir

and the root cause behind them is about ==Inductance==.

Traces on PCB in real life is not ideal. What I mean by "not ideal" is that every trace has inductance and resistance. The resistance usually has less impact, but the inductance can cause significant problems.

From my college textbook (quite a long time ago), the formula for an inductor:
$$ V=L\frac{di}{dt}$$

When an IC suddenly draws more current from the power rail (e.g., a MOSFET switching on/off), the change in current causes a voltage drop. This typically occurs over a very short period (on the nanosecond scale), resulting in a **sharp voltage edge**.

This sharp edge thing, what's the problem?  

1. It contains high frequency noise.
2. The power rail, usually is a long traces. With inductance on it, it will radiate. Become a source of EMI.
3. The voltage of the power rail drops. It can cause logic errors — e.g., a logic "HIGH" may be misread as "LOW", leading to unpredictable behavior.

This is where the decoupling capacitor steps in


## How to choose it (Value/Size/Placement)
### Placement
To deal with switching noise, **minimizing the loop inductance** is key.

Use the smallest package size possible, and place the capacitor as close to the IC’s power pin as you can.

### Value
To mitigate voltage drop caused by high di/dt, the required capacitance can be estimated using:

\begin{align*}
\Delta Q &= C \times \Delta V\\&=I \times \Delta t
\end{align*}

$$C = \frac{I \times \Delta t}{\Delta V}$$

Where:
$C$ : Capacitance of decoupling capacitor\\
$I$ : Transient current needed
$\Delta t$ : Rise time/Fall time
$\Delta V$ : The voltage drop that your design can tolerate

:::success
:pencil2: 
**Example**:
If we have an IC that controls 8 GPIOs from "LOW" to "HIGH". The current needed in total would be $100mA$. The fast edge driver switch in $2\space ns$. The supply voltage is $3.3V$ and we expect the voltage fluctuate no more than $5 \%$.
$$C=\frac{100mA \times2ns}{160mV}=1.25\space nF$$

Thus, any capacitor bigger than $1.25\space nF$ is suitable for your design.
:::


### Size
The smaller the capacitor package, the lower its **ESL (Equivalent Series Inductance)**. 
ESL is determined by physical size of a capacitor itself. 

For example,
A $0.1\space uF$ and $1\space uF$ in the same package size $0603$, the ESL is the roughly the same.

Choose a small package of MLCC with what you calculate.

:::info
:bulb: Capacitance is also limited by physical size, meaning, you can't really get a bulk capacitor with a tiny package. There is a limitation.
:::

## Summary
The concepts in this article all address one core issue: **loop inductance** present in PCB traces and IC pins.

The goal of placing decoupling capacitors is:
* To reduce loop inductance, and
* To supply instantaneous current during fast switching events.

Every design should be validated through testing. This article aims to provide a good estimation, but don't be constrained  by the formula.

I also recommend watching the Robert Feranec's youtube video. It really helps me to understand more about this seemingly mysterious topic.

## Reference
1. [What Decoupling Capacitor Value To Use And Where To Place Them | Eric Bogatin](https://www.youtube.com/watch?v=ARwBwHZESOY&t=2722s&ab_channel=RobertFeranec)
2. [The Myth of Three Capacitor Values](https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values)