---
# System prepended metadata

title: verilog lab7
tags: [digital system]

---

---
title: verilog lab7
tags: digital system
language: zh-tw
---
# verilog lab7
```verilog=
module ClockDivider(
    input wire rst,
    input wire clk,
    output reg clk_out
);
    reg [11:0] count;
    parameter DIVIDER = 2500; 

    always @(posedge clk) begin
        if (!rst) begin
            count <= 0;
            clk_out <= 0;
        end
        else begin
            if (count == DIVIDER - 1) begin
                count <= 0;
                clk_out <= ~clk_out;
            end
            else begin
                count <= count + 1;
            end
        end
    end
endmodule

module Display(
    input wire [3:0] count,
    output reg [6:0] out
);
    always @* begin
        case(count)
            4'b0000: out = 7'b1000000; // 0
            4'b0001: out = 7'b1111001; // 1
            4'b0010: out = 7'b0100100; // 2
            4'b0011: out = 7'b0110000; // 3
            4'b0100: out = 7'b0011001; // 4
            4'b0101: out = 7'b0010010; // 5
            4'b0110: out = 7'b0000010; // 6
            4'b0111: out = 7'b1111000; // 7
            4'b1000: out = 7'b0000000; // 8
            4'b1001: out = 7'b0010000; // 9
            4'b1010: out = 7'b0001000; // A
            4'b1011: out = 7'b0000011; // b
            4'b1100: out = 7'b1000110; // C
            4'b1101: out = 7'b0100001; // d
            4'b1110: out = 7'b0000110; // E
            4'b1111: out = 7'b0001110; // F
            default: out = 7'b1111111; 
        endcase
    end
endmodule

module lab_11(
    input wire CLOCK_50, // Clock
    input wire SW0,       // Reset
    output reg [7:0] dot_row, // Dots Rows
    output reg [7:0] dot_col, // Dots Columns
    output wire [6:0] HEX    // 7-displayer
);	
	 reg [1:0] stage;
    reg [2:0] row_cnt;
    reg [3:0] count;
	 wire clk_div;

    ClockDivider C_D(
        .rst(SW0),
        .clk(CLOCK_50),
        .clk_out(clk_div)
    );

    Display displayer (
        .count(count),
        .out(HEX)
    );
    reg [13:0] cnt;
    parameter range = 10000;
    
    always @(posedge clk_div or negedge SW0) begin
        if (~SW0) begin
            row_cnt <= 0;
				dot_row <= 8'b00000000;
				dot_col <= 8'b00000000;
            stage <= 2'b00; // Green stage
            count <= 10; // Initial count for green stage
        end
        else begin
            case (stage)
                2'b00: begin // Green stage
                    if (cnt == 0) begin
                        cnt <= cnt + 1;
                        count <= count - 1;
                    end
                    else begin
                        if (cnt == range - 1) begin
                            cnt <= 0;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                    if (count == 0 && cnt == range - 1) begin
                        stage <= 2'b01;
                        count <= 3; // Reset count
								cnt <= 1;
                    end 
                    else begin
                        row_cnt <= row_cnt + 1;
                    end
                    case (row_cnt)
                        3'd0 : dot_row <= 8'b01111111;
                        3'd1 : dot_row <= 8'b10111111;
                        3'd2 : dot_row <= 8'b11011111;
                        3'd3 : dot_row <= 8'b11101111;
                        3'd4 : dot_row <= 8'b11110111;
                        3'd5 : dot_row <= 8'b11111011;
                        3'd6 : dot_row <= 8'b11111101;
                        3'd7 : dot_row <= 8'b11111110;
                    endcase

                    case (row_cnt)
                        3'd0 : dot_col <= 8'b00001100;
                        3'd1 : dot_col <= 8'b00001100;
                        3'd2 : dot_col <= 8'b00011001;
                        3'd3 : dot_col <= 8'b01111110;
                        3'd4 : dot_col <= 8'b10011000;
                        3'd5 : dot_col <= 8'b00011000;
                        3'd6 : dot_col <= 8'b00101000;
                        3'd7 : dot_col <= 8'b01001000;
                    endcase
                end

                2'b01: begin // Yellow stage
                    if (cnt == 0) begin
                        cnt <= cnt + 1;
                        count <= count - 1;
                    end
                    else begin
                        if (cnt == range - 1) begin
                            cnt <= 0;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                    if (count == 0 && cnt == range - 1) begin
                        stage <= 2'b10;
                        count <= 15; // Reset count
								cnt <= 1;
                    end 
						  else begin
                        row_cnt <= row_cnt + 1;
                    end
                    case (row_cnt)
                        3'd0 : dot_row <= 8'b01111111;
                        3'd1 : dot_row <= 8'b10111111;
                        3'd2 : dot_row <= 8'b11011111;
                        3'd3 : dot_row <= 8'b11101111;
                        3'd4 : dot_row <= 8'b11110111;
                        3'd5 : dot_row <= 8'b11111011;
                        3'd6 : dot_row <= 8'b11111101;
                        3'd7 : dot_row <= 8'b11111110;
                    endcase

                    case (row_cnt)
                        3'd0 : dot_col <= 8'b00000000;
								3'd1 : dot_col <= 8'b00100100;
								3'd2 : dot_col <= 8'b00111100;
								3'd3 : dot_col <= 8'b10111101;
								3'd4 : dot_col <= 8'b11111111;
								3'd5 : dot_col <= 8'b00111100;
								3'd6 : dot_col <= 8'b00111100;
								3'd7 : dot_col <= 8'b00000000;
                    endcase
                end

                2'b10: begin // Red stage
                    if (cnt == 0) begin
                        cnt <= cnt + 1;
                        count <= count - 1;
                    end
                    else begin
                        if (cnt == range - 1) begin
                            cnt <= 0;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                    if (count == 0 && cnt == range - 1) begin
                        stage <= 2'b00;
                        count <= 10; // Reset count
								cnt <= 1;
                    end 
						  else begin
                        row_cnt <= row_cnt + 1;
                    end 
                    case (row_cnt)
                        3'd0 : dot_row <= 8'b01111111;
                        3'd1 : dot_row <= 8'b10111111;
                        3'd2 : dot_row <= 8'b11011111;
                        3'd3 : dot_row <= 8'b11101111;
                        3'd4 : dot_row <= 8'b11110111;
                        3'd5 : dot_row <= 8'b11111011;
                        3'd6 : dot_row <= 8'b11111101;
                        3'd7 : dot_row <= 8'b11111110;
                    endcase

                    case (row_cnt)
                        3'd0 : dot_col <= 8'b00011000;
								3'd1 : dot_col <= 8'b00011000;
								3'd2 : dot_col <= 8'b00111100;
								3'd3 : dot_col <= 8'b00111100;
								3'd4 : dot_col <= 8'b01011010;
								3'd5 : dot_col <= 8'b00011000;
								3'd6 : dot_col <= 8'b00011000;
								3'd7 : dot_col <= 8'b00100100;
                    endcase
                end

                default: begin //default
                    if (cnt == 0) begin
                        cnt <= cnt + 1;
                        count <= count - 1;
                    end
                    else begin
                        if (cnt == range - 1) begin
                            cnt <= 0;
                        end
                        else begin
                            cnt <= cnt + 1;
                        end
                    end
                    if (count == 0 && cnt == range - 1) begin
                        stage <= 2'b00;
                        count <= 10; // Reset count
								cnt <= 1;
                    end 
                    case (row_cnt)
                        3'd0 : dot_row <= 8'b00000000;
                        3'd1 : dot_row <= 8'b00000000;
                        3'd2 : dot_row <= 8'b00000000;
                        3'd3 : dot_row <= 8'b00000000;
                        3'd4 : dot_row <= 8'b00000000;
                        3'd5 : dot_row <= 8'b00000000;
                        3'd6 : dot_row <= 8'b00000000;
                        3'd7 : dot_row <= 8'b00000000;
                    endcase

                    case (row_cnt)
                        3'd0 : dot_col <= 8'b00000000;
                        3'd1 : dot_col <= 8'b00000000;
                        3'd2 : dot_col <= 8'b00000000;
                        3'd3 : dot_col <= 8'b00000000;
                        3'd4 : dot_col <= 8'b00000000;
                        3'd5 : dot_col <= 8'b00000000;
                        3'd6 : dot_col <= 8'b00000000;
                        3'd7 : dot_col <= 8'b00000000;
                    endcase
                end
            endcase
        end
    end
endmodule

```
:::spoiler
```verilog=
//green light
case (row_cnt)
    3'd0 : dot_row <= 8'b01111111;
    3'd1 : dot_row <= 8'b10111111;
    3'd2 : dot_row <= 8'b11011111;
    3'd3 : dot_row <= 8'b11101111;
    3'd4 : dot_row <= 8'b11110111;
    3'd5 : dot_row <= 8'b11111011;
    3'd6 : dot_row <= 8'b11111101;
    3'd7 : dot_row <= 8'b11111110;
endcase

case (row_cnt)
    3'd0 : dot_col <= 8'b00001100;
    3'd1 : dot_col <= 8'b00001100;
    3'd2 : dot_col <= 8'b00011001;
    3'd3 : dot_col <= 8'b01111110;
    3'd4 : dot_col <= 8'b10011000;
    3'd5 : dot_col <= 8'b00011000;
    3'd6 : dot_col <= 8'b00101000;
    3'd7 : dot_col <= 8'b01001000;
endcase

//yellow light
case (row_cnt)
    3'd0 : dot_row <= 8'b01111111;
    3'd1 : dot_row <= 8'b10111111;
    3'd2 : dot_row <= 8'b11011111;
    3'd3 : dot_row <= 8'b11101111;
    3'd4 : dot_row <= 8'b11110111;
    3'd5 : dot_row <= 8'b11111011;
    3'd6 : dot_row <= 8'b11111101;
    3'd7 : dot_row <= 8'b11111110;
endcase

case (row_cnt)
    3'd0 : dot_col <= 8'b00000000;
    3'd1 : dot_col <= 8'b00100100;
    3'd2 : dot_col <= 8'b00111100;
    3'd3 : dot_col <= 8'b10111101;
    3'd4 : dot_col <= 8'b11111111;
    3'd5 : dot_col <= 8'b00111100;
    3'd6 : dot_col <= 8'b00111100;
    3'd7 : dot_col <= 8'b00000000;
endcase

//red light
case (row_cnt)
    3'd0 : dot_row <= 8'b01111111;
    3'd1 : dot_row <= 8'b10111111;
    3'd2 : dot_row <= 8'b11011111;
    3'd3 : dot_row <= 8'b11101111;
    3'd4 : dot_row <= 8'b11110111;
    3'd5 : dot_row <= 8'b11111011;
    3'd6 : dot_row <= 8'b11111101;
    3'd7 : dot_row <= 8'b11111110;
endcase

case (row_cnt)
    3'd0 : dot_col <= 8'b00011000;
    3'd1 : dot_col <= 8'b00011000;
    3'd2 : dot_col <= 8'b00111100;
    3'd3 : dot_col <= 8'b00111100;
    3'd4 : dot_col <= 8'b01011010;
    3'd5 : dot_col <= 8'b00011000;
    3'd6 : dot_col <= 8'b00011000;
    3'd7 : dot_col <= 8'b00100100;
endcase
```
:::





