# Assignment3: SoftCPU
###### tags:`computer architure`
## Assignment
### makefile
#### Rewrite C code
* change ```int``` and ```char``` into ```volatile int``` and ```volatile char```
* In function printf need to add ```\n``` in the end of sentance.
```c=
#include <stdio.h>
volatile int ispower2(volatile int n){
while(n){
if(n==1) return 1;
if(n%2) return 0;
n/=2;
}
return n==1;
}
int main(){
volatile int ans = ispower2(5);
printf("\n%d \n",ans);
return 0;
}
```
#### Process of Compiling in RISC-V
1. create a new folder under sw and put c code inside.
2. copy makefile and syscall.c in dhrystone to the new folder just been created.
3. change MakeFile
```
SRC = test1.c syscall.c
TARGET = test1
```
4. go to srv32 enter the command
```makefile hw3```
5. get the result
RTL result
> Get the location ~srv32/sim/
> Use the command to run RTL simulator
```
$ make hw3.run
```
get the result
```
0
Excuting 1468 instructions, 1900 cycles, 1.294 CPI
Program terminate
- ../rtl/../testbench/testbench.v:418: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.025 s
Simulation cycles: 1911
Simulation speed : 0.07644 MHz
```
ISS result
> Get the location ~srv32/tools/
> Use the command to run ISS simulator
```
$ make hw3.run
```
get the result
```
./rvsim --memsize 128 -l trace.log ../sw/hw3/hw3.elf
0
Excuting 1468 instructions, 1900 cycles, 1.294 CPI
Program terminate
Simulation statistics
=====================
Simulation time : 0.002 s
Simulation cycles: 1900
Simulation speed : 0.903 MHz
```
### Analyze srv32 Waveform
#### Pipeline structure
srv32 is a RISCV 3-stage pipeline processor.
The picture underneath shows the datapath of srv32.
#### Waveform analyze
open the .dis file in hw3
```
00000000 <_start>:
0: 00014297 auipc t0,0x14
4: 52028293 addi t0,t0,1312 # 14520 <trap_handler>
8: 30529073 csrw mtvec,t0
c: 3050e073 csrsi mtvec,1
10: 00022297 auipc t0,0x22
14: 84428293 addi t0,t0,-1980 # 21854 <_PathLocale>
18: 00022317 auipc t1,0x22
1c: 87c30313 addi t1,t1,-1924 # 21894 <_bss_end>
...
```
I took ```addi t0,t0,1312``` as the target to analyze how the datas go in three stage pipeline.
Open the ```wave.fst``` in GTKwave.
We can find out before the cik clock,```imem_addr``` got the first instruction and data ```00014297```, when ```t = 0 ```,```imem_addr```pass the data ```00014297``` to ```inst```
imem_addr seems to be the IF stage which calculate the address of instruction.
imem_rdataćinst and imm are the ID stage which pass and decode the instruction and data location to the next stage.
we can see our target instruction be pass when the next clk clock.
That's see next stage.
when time is 45ps
we can see ex_imm is the number 1312 that will add to t0,and reg_rdata1 will be t0, in this stage ALU will add ex_imm to ex_result ,that will be 00014000+0000520=00014520
And the final stage,
ex_result will pass the data to wb_result as the assambly dst ,then will store the data into register
as the material shows,we can sum up the few result:
``` addi dst rs1 imm```
1. First, the pc will store in imem_addr, when the clk clock imem_addr will add 4 to get the next instruction address
2. as the same time, imem_rdata will been decode to instr which is represent the insturetion and imm represent the data need to be deal
3. Second,reg_rdata1 as the assembly code rs1, imm and rs1 will been calculate by ALU and the result will pass to ex_result.
4. Third, the ex_reslut will pass the data to wb_result it means dst in assembly code, then write back to the dst.
### Optimization
#### change c code
I change code into bitwise version
```clike=
#include <stdio.h>
volatile int ispower2(volatile int n){
return n>0 && !(n&(n-1));
}
int main(){
volatile int ans = ispower2(5);
printf("\n%d \n",ans);
return 0;
}
```
and the result shows below
```
0
Excuting 1468 instructions, 1900 cycles, 1.294 CPI
Program terminate
- ../rtl/../testbench/testbench.v:418: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.022 s
Simulation cycles: 1911
Simulation speed : 0.0868636 MHz
```
### Summary
compare the result
||Original|Bitwise|
|---|---|---|
|Simulation Time|0.027s|0.002s|
|Simulation Cycles|1931|1911|
|Executing Instructions|1480|1468|
|Executions Cycles|1920|1900|
|CPI|1.297|1.294|
## How Does RISC-V Compliance Tests Works
The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant.
The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant.
## Why the signature should be matched
Signature is defined memory area where the result of a test suite been stored ,so we need to ensure the processor work correctly when different types of instructions been excuted.
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