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# System prepended metadata

title: '#Lab 8'

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# Lab 8

## Question-1:
Design a Full Adder from 2-Half Adders using Verilog. And, verify your design by writing test bench for all the possible permutations of input. 

## Question-2:

Design a 4-bit Ripple Carry Adder using Verilog. And, verify your design by writing test bench for some of the possible permutations of input. 

## Question-3:

Design a 2:1 multiplexer using Structural Modelling. And, verify your design by writing test bench for all the possible permutations of input. 

## Question-4:

### Not for evalauation:

We will be using Champsim for the next few labs.
https://github.com/ChampSim/ChampSim.git
Clone the repository and compile the code.
The repository has instructions in detail as to how to do it.
Change the LRU policy to MRU.
Run one trace, and compare the IPC with LRU.