---
# System prepended metadata

title: lab1

---

# lab1
## using gate-level
```verilog=
module MultiplesDetector_G(in, out);

    parameter n = 4 ;

    //io_port
    input [n-1: 0]in;
    output out;

    //saver
    wire not_a, not_b, not_c;
    wire and0, and1, and2, and3;

    not not_gate0(not_a, in[3]);
    not not_gate1(not_b, in[2]);
    not not_gate2(not_c, in[1]);
    not not_gate3(not_d, in[0]);

    and and_gate0(and0, not_d);
    and and_gate1(and1, not_a, not_b, in[1]);
    and and_gate2(and2, in[3], in[2], in[1]);
    and and_gate3(and3, in[3], not_b, not_c);

    or or_gate(out, and0, and1, and2, and3);


endmodule
```
## dataflow
```verilog!
module MultiplesDetector_D(in, out);
// d'+a'b'c+abc+ab'c'
    parameter n = 4;

    //io_port
    input [n-1: 0]in;
    output out;

    assign out = (!in[0])
                | (!in[3] & !in[2] & in[1])
                | (in[3] & in[2] & in[1])
                | (in[3] & !in[2] & !in[1]);

endmodule
```
## behavioral
```verilog=
module MultiplesDetector_B(in, out);

    parameter n = 4;

    //io_port
    input [n-1: 0]in;
    output out;
    reg out;
    always @(*) begin
        case(in)
            0, 2, 3, 4, 6, 8,9, 10, 12, 14, 15:begin
                out = 1'b1;
            end
            default:begin
                out = 1'b0;
            end
        endcase
    end

endmodule
```
## testbench
```verilog=
module MultiplesDetector_tb;
    parameter delay = 5;

    wire out_G, out_D, out_B;
    reg [3: 0]in;
    integer i;

    wire is;

    assign is = in == 0 || in == 2 || in == 3 || in == 4 || in == 6 || in == 8 || in == 9 || in == 10 || in == 12 || in == 14 || in == 15;


    initial begin
    in = 4'd0;
        for(i = 0; i < 16; i = i + 1)begin
            #delay
            $display("time = %4d, in = %b, out_G = %b, out_D = %b, out_B = %b",
                    $time, in, out_G, out_D, out_B);
            if((out_G === 1'bx | out_D === 1'bx | out_B === 1'bx |
                out_G === 1'bz | out_D === 1'bz | out_B === 1'bz ) ||
                ( is && (out_G & out_D & out_B) == 0)||
                (!is && (out_G & out_D & out_B) == 1))
                begin
                    $display("you got wrong answer!!");
                    $finish;
                end
            in = in + 4'd1;
        end
        $display("congratulations!!");
        $finish;
    end

    MultiplesDetector_G hvg( .in(in), .out(out_G) );
    MultiplesDetector_D hvd( .in(in), .out(out_D) );
    MultiplesDetector_B hvb( .in(in), .out(out_B) );


endmodule
```