# Lab 10 and 11

module full_adder(
  input a, b, cin,
  output sum, cout
);
  
  assign {sum, cout} = {a^b^cin, ((a & b) | (b & cin) | (a & cin))};
 
endmodule

module ripple_carry_adder_subtractor #(parameter SIZE = 4) (
  input [SIZE-1:0] A, B, 
  input CTRL,
  output [SIZE-1:0] S, Cout);
  bit [SIZE-1:0] Bc;
  genvar g;
  
  assign Bc[0] = B[0] ^ CTRL;
    
  full_adder fa0(A[0], Bc[0], CTRL, S[0], Cout[0]);
  generate  
    for(g = 1; g<SIZE; g++) begin
      assign Bc[g] = B[g] ^ CTRL;
      full_adder fa(A[g], Bc[g], Cout[g-1], S[g], Cout[g]);
    end
  endgenerate
endmodule

module halfadder(a,b,out,carry);
input a,b;
output out,carry;
assign out=a^b;
and (carry,a,b);
endmodule

module fulladder(a,b,c,out,carry);
input a,b,c;
output out,carry;
wire w1,w2,w3;
halfadder h1 (a,b,w1,w2);
halfadder h2 (w1,c,out,w3);
or (carry,w2,w3);
endmodule

module rippleadder(
    input [31:0] a, b,
    input c,
    output [31:0] out,
    output carry
);

wire [31:0] w;
wire [31:0] w_temp;

assign w_temp = c ^ b;

assign w[0] = c^b[0];
assign w[1] = c^ b[1];
assign w[2] = c^ b[2];
assign w[3] = c^ b[3];
assign w[4] = c^ b[4];
assign w[5] = c^ b[5];
assign w[6] = c^ b[6];
assign w[7] = c^ b[7];
assign w[8] = c^ b[8];
assign w[9] = c^ b[9];
assign w[10] = c ^ b[10];
assign w[11] = c^ b[11];
assign w[12] = c ^ b[12];
assign w[13] = c^ b[13];
assign w[14] = c ^ b[14];
assign w[15] = c ^ b[15];
assign w[16] =c^ b[16];
assign w[17] = c ^ b[17];
assign w[18] = c^ b[18];
assign w[19] = c^ b[19];
assign w[20] = c^ b[20];
assign w[21] = c ^ b[21];
assign w[22] = c^ b[22];
assign w[23] = c^ b[23];
assign w[24] = c^ b[24];
assign w[25] = c^ b[25];
assign w[26] = c ^ b[26];
assign w[27] = c^ b[27];
assign w[28] = c^ b[28];
assign w[29] = c ^ b[29];
assign w[30] = c ^ b[30];
assign w[31] = c ^ b[31];

fulladder f1(a[0], w[0], c, out[0], w1);
fulladder f2(a[1], w[1], w1, out[1], w2);
fulladder f3(a[2], w[2], w2, out[2], w3);
fulladder f4(a[3], w[3], w3, out[3], w4);
fulladder f5(a[4], w[4], w4, out[4], w5);
fulladder f6(a[5], w[5], w5, out[5], w6);
fulladder f7(a[6], w[6], w6, out[6], w7);
fulladder f8(a[7], w[7], w7, out[7], w8);
fulladder f9(a[8], w[8], w8, out[8], w9);
fulladder f10(a[9], w[9], w9, out[9], w10);
fulladder f11(a[10], w[10], w10, out[10], w11);
fulladder f12(a[11], w[11], w11, out[11], w12);
fulladder f13(a[12], w[12], w12, out[12], w13);
fulladder f14(a[13], w[13], w13, out[13], w14);
fulladder f15(a[14], w[14], w14, out[14], w15);
fulladder f16(a[15], w[15], w15, out[15], w16);
fulladder f17(a[16], w[16], w16, out[16], w17);
fulladder f18(a[17], w[17], w17, out[17], w18);
fulladder f19(a[18], w[18], w18, out[18], w19);
fulladder f20(a[19], w[19], w19, out[19], w20);
fulladder f21(a[20], w[20], w20, out[20], w21);
fulladder f22(a[21], w[21], w21, out[21], w22);
fulladder f23(a[22], w[22], w22, out[22], w23);
fulladder f24(a[23], w[23], w23, out[23], w24);
fulladder f25(a[24], w[24], w24, out[24], w25);
fulladder f26(a[25], w[25], w25, out[25], w26);
fulladder f27(a[26], w[26], w26, out[26], w27);
fulladder f28(a[27], w[27], w27, out[27], w28);
fulladder f29(a[28], w[28], w28, out[28], w29);
fulladder f30(a[29], w[29], w29, out[29], w30);
fulladder f31(a[30], w[30], w30, out[30], w31);
fulladder f32(a[31], w[31], w31, out[31], carry);

endmodule

module alu (
    input [31:0] a, b,
    input [31:0] s,
    output [31:0] out
);

wire [31:0] i1, i2, i3, i4, i5, i6, i7, i8, i9, i10;
wire w;
assign w = 1'b0;

rippleadder utt(a, b, w, i1, w3);
rippleadder utt1(a, b, 1'b1, i2, w4);

assign i3 = a | b; // Bitwise OR
assign i4 = a & b; // Bitwise AND
assign i5 = a ^ b; // XOR
assign i6 = a << b; // Shift Left Logical
assign i7 = a >> b; // Shift Right Logical
assign i8 = a >>> b; // Shift Right Arithmetic
assign i9 = (a < b) ? 1 : 0; // Set Less Than
assign i10 = (a < b) ? 1 : 0; // Set Less Than (U)

assign out = !s[0] ? (!s[1] ? i1 : i3) : (!s[1] ? i2 : i4);

endmodule

module alu_tb;

Test bench

  reg [31:0] a, b;
    reg [31:0] s;
    wire [31:0] out;
    
    alu uut (
        .a(a),
        .b(b),
        .s(s),
        .out(out)
    );
    
    initial begin
        a = 32'd10;
        b = 32'd5;
        s = 32'b00000000000000000000000000000001; // For addition
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000011; // For subtraction
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000010; // For bitwise OR
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000011; // For bitwise AND
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        // Additional instructions testing
        s = 32'b00000000000000000000000000000100; // XOR
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000101; // Shift Left Logical
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000110; // Shift Right Logical
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000000111; // Shift Right Arithmetic
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000001000; // Set Less Than
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
        s = 32'b00000000000000000000000000001001; // Set Less Than (U)
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);
        
       
        $finish;
    end
endmodule

Process verilog code

module alu (
    input logic [31:0] a, b,
    input logic [3:0] s,
    output logic [31:0] out
);

always_comb begin
    case(s)
        4'b0001: out = a + b; // Addition
        4'b0010: out = a - b; // Subtraction
        4'b0011: out = a | b; // Bitwise OR
        4'b0100: out = a & b; // Bitwise AND
        4'b0101: out = a ^ b; // XOR
        4'b0110: out = a << b; // Shift Left Logical
        4'b0111: out = a >>> b; // Shift Right Arithmetic
        4'b1000: out = (a < b) ? 32'h1 : 32'h0; // Set Less Than (signed)
        4'b1001: out = ($unsigned(a) < $unsigned(b)) ? 32'h1 : 32'h0; // Set Less Than (unsigned)
        default: out = 32'h0; // Default behavior
    endcase
end

endmodule

module alu_tb;
    logic [31:0] a, b;
    logic [3:0] s;
    logic [31:0] out;

    alu uut (
        .a(a),
        .b(b),
        .s(s),
        .out(out)
    );

    initial begin
        a = 32'd10;
        b = 32'd5;
        s = 4'b0001; // For addition
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b0010; // For subtraction
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        // Additional instructions testing
        s = 4'b0011; // For bitwise OR
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b0100; // For bitwise AND
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b0101; // XOR
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b0110; // Shift Left Logical
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b0111; // Shift Right Arithmetic
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b1000; // Set Less Than (signed)
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        s = 4'b1001; // Set Less Than (unsigned)
        $display("a = %d, b = %d, s = %b, out = %d", a, b, s, out);

        $finish;
    end
endmodule