# Lab 8
Name: Bilwani k
Roll no.: CS22B013

---
## Question 1
**Code of a full adder with two half adders**

module Full_Adder(a, b, cin, Sum, Cout);

input a, b, cin; 
output Sum, Cout; 

wire S0, C1;
wire C2;

// Call Half Adder
Half_Adder HA1 (.a(a), .b(b), .Sum(S0), .Cout(C1));

Half_Adder HA2 (.a(cin), .b(S0), .Sum(Sum), .Cout(C2));

OR_2in R1 (.a(C1),.b(C2), .y(Cout));

endmodule

**Test bench code**

module test_full_adder;
    reg a, b, cin;
    wire Sum, Cout;
    
    Full_Adder FA (.a(a), .b(b), .cin(cin), .Sum(Sum), .Cout(Cout));
    
    initial begin
        $display("A B Cin | Sum Cout");
        $display("---------|--------");
        
        // Test all possible input combinations
        a = 0; b = 0; cin = 0; #10;
        a = 0; b = 0; cin = 1; #10;
        a = 0; b = 1; cin = 0; #10;
        a = 0; b = 1; cin = 1; #10;
        a = 1; b = 0; cin = 0; #10;
        a = 1; b = 0; cin = 1; #10;
        a = 1; b = 1; cin = 0; #10;
        a = 1; b = 1; cin = 1; #10;
        
        $finish;
    end
endmodule

---

## Question 2
**Code for 4 bit Ripple carry**

module rca(s,c,a,b,cin);
input[3:0]a,b;
input cin;
output[3:0]s;
output c;
wire c0,c1,c2;

fa g1(s[0],c0,a[0],b[0],cin);
fa g2(s[1],c1,a[1],b[1],c0);
fa g3(s[2],c2,a[2],b[2],c1);
fa g4(s[3],c,a[3],b[3],c2);
 endmodule

**Test bench**

module rca_tb;

reg [3:0] a;
reg [3:0] b;
reg cin;

wire [3:0] s;
wire c;

rca uut (
.s(s),
.c(c),
.a(a),
.b(b),
.cin(cin)
);

a=4'b0001;
b=4'b1001;
cin=0;

#100
a=4'b0011;
b=4'b1001;
cin = 0;

end 
endmodule 

---

## Question 3

**Code for 2:1 Mux**

module MUX_2in_Nbit #(parameter N = 8) (a,b,s,y);

input [N-1:0]a;
input [N-1:0]b;

input wire s;

output [N-1:0]y;   // Y = (s_bar AND a ) OR (s AND b ) = Y_r OR Y_l

assign y = s?b:a;  
endmodule

**Test bench**

module mux21_df_bench();
    reg [1:0] a1; 
    reg [1:0] b1;
    reg s1; 
    wire [1:0] y1;

    MUX_2in_Nbit #(2) dUT_1 (.a(a1), .b(b1), .s(s1), .y(y1));

    initial begin
        $display("a b s | y");
        $display("-------|---");
        a1 = 2'b00; b1 = 2'b00; s1 = 0; #10;
        a1 = 2'b00; b1 = 2'b01; s1 = 0; #10;
        a1 = 2'b00; b1 = 2'b10; s1 = 0; #10;
        a1 = 2'b00; b1 = 2'b11; s1 = 0; #10;
        a1 = 2'b01; b1 = 2'b00; s1 = 1; #10;
        a1 = 2'b01; b1 = 2'b01; s1 = 1; #10;
        a1 = 2'b01; b1 = 2'b10; s1 = 1; #10;
        a1 = 2'b01; b1 = 2'b11; s1 = 1; #10;
        $finish;
    end
endmodule